Patents by Inventor Yuji Akashi
Yuji Akashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240138263Abstract: A light emitting element of one or more embodiments includes a first electrode, a second electrode oppositely to the first electrode, and an emission layer between the first electrode and the second electrode. The light emitting element of one or more embodiments includes a polycyclic compound represented by a specific chemical structure in the emission layer, thereby showing improved emission efficiency and life characteristics.Type: ApplicationFiled: September 18, 2023Publication date: April 25, 2024Inventors: Makoto YAMAMOTO, Keigo HOSHI, Yuji SUZAKI, Hirokazu KUWABARA, Nobutaka AKASHI, Ryuhei FURUE, Toshiyuki MATSUURA, Yoshiro SUGITA, Yuma AOKI, Yuuki MIYAZAKI
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Publication number: 20060108677Abstract: A lower chip is fixed to a surface of an interposer by flip-chip bonding with an under fill acting as an adhesive applied to the surface. A lifted pad having a height of approximately 10 ?m is provided on the surface of the interposer. A bonding wire connects the lifted pad and a bonding pad provided on a surface of an upper chip. A stick-out portion of the under fill at the time of fixing the lower chip to the interposer is dammed by the lifted portion of the lifted pad. This prevents the stick-out portion of the under fill from covering the top of the lifted pad.Type: ApplicationFiled: October 28, 2005Publication date: May 25, 2006Inventors: Mitsutaka Ikeda, Katsuhito Kikuma, Sachiko Nogami, Yuji Akashi
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Patent number: 6818999Abstract: A semiconductor device of MCP structure, in which multiple semiconductor chips are provided in a single package and a method of manufacturing the same, that prevents damage of semiconductor chip that does not require burn-in and ensures the initial reliability of the semiconductor chip that requires the burn-in, are provided. The method has the steps of resin sealing and packaging the semiconductor chip that requires the burn-in and performing the burn-in to such packaged semiconductor chip; and mounting the semiconductor chip evaluated to be non-defective in the burn-in to the substrate along with the semiconductor chip not requiring the burn-in.Type: GrantFiled: January 10, 2003Date of Patent: November 16, 2004Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Yuji Akashi, Takeshi Ikuta
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Patent number: 6777799Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: July 22, 2003Date of Patent: August 17, 2004Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Takao Nishimura
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Publication number: 20040051119Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: July 22, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Takao Nishimura
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Publication number: 20030180988Abstract: A semiconductor device of MCP structure, in which multiple semiconductor chips are provided in a single package and a method of manufacturing the same, that prevents damage of semiconductor chip that does not require burn-in and ensures the initial reliability of the semiconductor chip that requires the burn-in, are provided. The method has the steps of resin sealing and packaging the semiconductor chip that requires the burn-in and performing the burn-in to such packaged semiconductor chip; and mounting the semiconductor chip evaluated to be non-defective in the burn-in to the substrate along with the semiconductor chip not requiring the burn-in.Type: ApplicationFiled: January 10, 2003Publication date: September 25, 2003Inventors: Katsuhito Kikuma, Yuji Akashi, Takeshi Ikuta
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Patent number: 6621169Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: GrantFiled: August 29, 2001Date of Patent: September 16, 2003Assignee: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Publication number: 20020027295Abstract: In a stacked semiconductor device which has a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a flexible printed wiring board provided with external connecting terminals. A printed circuit board is placed and mounted on the first semiconductor chip by flip-chip bonding. A second semiconductor chip is secured onto the printed circuit board. The second semiconductor chip is connected to the flexible printed wiring board by wire bonding. The first semiconductor chip is connected to the flexible printed wiring board by wire bonding via the printed circuit board.Type: ApplicationFiled: August 29, 2001Publication date: March 7, 2002Applicant: Fujitsu LimitedInventors: Katsuhito Kikuma, Mitsutaka Ikeda, Yoshihiro Tsukidate, Yuji Akashi, Kaname Ozawa, Akira Takashima, Tadashi Uno, Takao Nishimura, Fumihiko Ando, Hiroshi Onodera, Hayato Okuda
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Patent number: 6316838Abstract: A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.Type: GrantFiled: March 20, 2000Date of Patent: November 13, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Tetsuya Hiraoka, Mitsutaka Sato, Yuji Akashi, Akira Okada, Masahiko Harayama
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Patent number: 6215182Abstract: A semiconductor device includes the first through third semiconductor devices which are stacked on a substrate and the first through third wires for connecting the semiconductor elements and the substrate. The first wires serve to connect electrodes of the first semiconductor element positioned uppermost and electrodes of the second semiconductor element. The second wires serve to connect the electrodes of the second semiconductor element and electrodes of the third semiconductor element. The third wires serve to connect the electrodes of the third semiconductor element and bonding pads of the substrate. Between the first wires and the electrodes of the second semiconductor element and between the second wires and the electrodes of the third semiconductor element, stud bumps are provided so as to form space therebetween, thereby avoiding short-circuits therebetween.Type: GrantFiled: March 20, 2000Date of Patent: April 10, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Ryuji Nomoto, Yuji Akashi, Katsuro Hiraiwa
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Patent number: 6111312Abstract: A semiconductor device is provided. This semiconductor device includes a resin package, a semiconductor chip, and leads consisting of inner leads and outer leads. The rear surface of the semiconductor chip and the inner leads are situated substantially on the same plane. The resin package is provided with notches on its mounting surface. The outer leads are bent inward along the exterior of the resin package and pulled around to the mounting surface, so that the edges of the outer leads are engaged with the notches.Type: GrantFiled: June 2, 1999Date of Patent: August 29, 2000Assignee: Fujitsu LimitedInventors: Yosuke Hirumuta, Yuji Akashi, Susumu Kida
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Patent number: 4838562Abstract: In chucking, a workpiece is clamped while drawn to the chuck body for positive contact of the workpiece to stoppers, whereby a degree of machining accuracy is remarkably improved.Type: GrantFiled: March 4, 1988Date of Patent: June 13, 1989Assignee: Yugen Kaisha Akashi TekkoshoInventor: Yuji Akashi