Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Abstract: A DRAM has memory cells provided at crossing points between word line conductors and bit line conductors. Each memory cell has a cell selection transistor and an information storage capacitor arranged over the bit line conductors. Unit active regions are defined in a main surface of a semiconductor substrate by a field isolation pattern. The field isolation pattern has a controlled length of extension of bird's beaks so that channel formation regions in each unit active region has almost no stepped portion to provide the cell selection transistors with a stabilized threshold voltage.

Abstract: A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.