Patents by Inventor Yuji Fukano

Yuji Fukano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200369243
    Abstract: An on-board device includes a storage unit that stores biometric information of a user of a vehicle that is used for authentication, and a control unit that increases difficulty of authenticating biometric information not having been used for authentication for a predetermined period or deletes such biometric information from the storage unit.
    Type: Application
    Filed: November 16, 2018
    Publication date: November 26, 2020
    Inventors: Rijin OWAKI, Yosuke OHASHI, Fumitaka YOSHIKAWA, Yuji FUKANO
  • Patent number: 10833100
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 10, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Publication number: 20200258876
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Application
    Filed: April 14, 2020
    Publication date: August 13, 2020
    Inventors: Naohiro HOSODA, Kazuma SHIMAMOTO, Tetsuya SHIRASU, Yuji FUKANO, Akio NISHIDA
  • Publication number: 20200251485
    Abstract: A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Manabu KAKAZU, Takashi YUDA, Yuji FUKANO
  • Publication number: 20200235123
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 23, 2020
    Inventors: Kenji SUGIURA, Mitsuteru MUSHIGA, Yuji FUKANO, Akio NISHIDA
  • Publication number: 20200227397
    Abstract: Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Shinsuke YADA, Masanori TSUTSUMI, Sayako NAGAMINE, Yuji FUKANO, Akio NISHIDA, Christopher J. PETTI
  • Patent number: 10665607
    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kenji Sugiura, Mitsuteru Mushiga, Yuji Fukano, Akio Nishida
  • Patent number: 10665580
    Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 26, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Kazuma Shimamoto, Tetsuya Shirasu, Yuji Fukano, Akio Nishida
  • Patent number: 10533971
    Abstract: A biosensor, including: a first cover member comprising an element-accommodating recess in an upper face thereof; a detection element using a surface acoustic wave, the detection element including an element substrate accommodated in the element-accommodating recess, and at least one detection unit located on an upper face of the element substrate configured to perform detection of an analyte; and a second cover member joined to the first cover member and covering the detection element, and including an inflow port from which the analyte flows in and a groove which extends from the inflow port to at least above the at least one detection unit and constitutes a capillary.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 14, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Atsuomi Fukuura, Toru Fukano, Yuji Kishida, Hiroyasu Tanaka, Hideharu Kurioka
  • Patent number: 10347647
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Keisuke Shigemura, Junichi Ariyoshi, Kazuki Kajitani, Yuji Fukano
  • Publication number: 20190198515
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Naohiro HOSODA, Keisuke SHIGEMURA, Junichi ARIYOSHI, Kazuki KAJITANI, Yuji FUKANO
  • Publication number: 20180342531
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.
    Type: Application
    Filed: May 29, 2017
    Publication date: November 29, 2018
    Inventors: Hiromasa Susuki, Masanori Tsutsumi, Shigehisa Inoue, Junji Oh, Kensuke Yamaguchi, Seiji Shimabukuro, Yuji Fukano, Ryoichi Ehara, Youko Furihata
  • Patent number: 10141331
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: November 27, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiromasa Susuki, Masanori Tsutsumi, Shigehisa Inoue, Junji Oh, Kensuke Yamaguchi, Seiji Shimabukuro, Yuji Fukano, Ryoichi Ehara, Youko Furihata
  • Patent number: 9711532
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Masato Miyamoto, Yuji Fukano
  • Publication number: 20170033121
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Applicant: SanDisk Technologies LLC
    Inventors: Masato Miyamoto, Yuji Fukano
  • Patent number: 9530781
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 27, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Masato Miyamoto, Yuji Fukano
  • Publication number: 20160181264
    Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Masato Miyamoto, Yuji Fukano
  • Publication number: 20160111436
    Abstract: A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: Hao DING, Masahiro YAEGASHI, Shigehiro FUJINO, Shuji MINAGAWA, Yuji FUKANO
  • Patent number: 9305934
    Abstract: A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 5, 2016
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Hao Ding, Masahiro Yaegashi, Shigehiro Fujino, Shuji Minagawa, Yuji Fukano
  • Patent number: 7254466
    Abstract: An engine start controller shortens the time required from when an operation switch is operated to when an engine is started. The engine start controller controls starting of the engine of a vehicle and power supply to an electric device system. A control unit selectively locks the steering shaft of the vehicle and performs authentication with a portable device, which is carried by a user of the vehicle, for permitting use of the vehicle. An operation switch is connected to the control unit and generates an operation signal when operated by the user. The control unit unlocks the steering shaft in parallel with supplying power to the electric device system when the operation signal is generated and use of the vehicle is permitted through the authentication.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: August 7, 2007
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventors: Hiroshi Mori, Toru Maeda, Yuji Fukano, Tomoo Kakegawa, Tomoyuki Funayama, Takashi Yanatsubo