Abstract: A reference current source includes a reference current path, a first output current path and a second output current path. The reference current path includes a diode-connected first transistor, a diode-connected second transistor, and a first resistor that are connected in series between a first fixed potential and a second fixed potential. The first output current path includes a third transistor having a gate connected to a gate of the second transistor, forming a current mirror together with the second transistor, and a second resistor interposed between the third transistor and the first fixed potential. The second output current path includes a voltage-current conversion circuit to which a potential of a third node between the third transistor and the second resistor in the first output current path is applied and through which a reference current flows.

Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.

Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: The present disclosure relates to an image sensor, an electronic device, and a method for generating a tessellation tile that allows pattern noise that can be generated in an image output from an image sensor including column ADCs or area ADCs to be less visible. An image sensor according to a first aspect of the present disclosure includes analog digital converters (ADCs), each of the ADCs being provided for a column, wherein the ADCs associated with the respective columns are configured to read charge signals simultaneously from pixels arranged on lines different from one another of the respectively associated columns, the number of ADCs being a predetermined number corresponding to the number of columns, the columns being adjacent to one another. The present disclosure is applicable to any electronic device including an image sensor.

Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.

Abstract: An image sensor includes a capacitor, a low-impedance virtual battery, and a boost current source. The capacitor includes one end connected to a vertical signal line and the other end. The low-impedance virtual battery is connected to the other end of the capacitor and configured to detect a current flowing in the capacitor. The boost current source is configured to provide a boost current to the vertical signal line, the boost current being a current corresponding to the current flowing in the capacitor.

Abstract: A solid-state imaging device includes: pixel signal reading lines; a pixel unit in which pixels including photoelectric conversion elements are arranged; and a pixel signal reading unit performing reading of pixel signals from the pixel unit through the pixel signal reading lines, wherein the pixel signal reading unit includes current source circuits each of which includes a load element as a current source connected to the pixel signal reading line forming a source follower, and the current source circuit includes a circuit generating electric current according to a slew rate of the pixel signal reading line and replicating electric current corresponding to the above electric current to flow in the current source.

Abstract: There is provided a current mirror that includes at least one bias amplifier configured to adjust a gate line voltage by feeding currents to the gate line to make constant gate-source voltages of a plurality of FETs (Field Effect Transistors), the gate line connecting gates of the FETs each being a load component in the current mirror.

Abstract: The present disclosure relates to an image sensor, an electronic device, and a method for generating a tessellation tile that allows pattern noise that can be generated in an image output from an image sensor including column ADCs or area ADCs to be less visible. An image sensor according to a first aspect of the present disclosure includes analog digital converters (ADCs), each of the ADCs being provided for a column, wherein the ADCs associated with the respective columns are configured to read charge signals simultaneously from pixels arranged on lines different from one another of the respectively associated columns, the number of ADCs being a predetermined number corresponding to the number of columns, the columns being adjacent to one another. The present disclosure is applicable to any electronic device including an image sensor.

Abstract: A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

Abstract: A solid-state imaging device includes: pixel signal reading lines; a pixel unit in which pixels including photoelectric conversion elements are arranged; and a pixel signal reading unit performing reading of pixel signals from the pixel unit through the pixel signal reading lines, wherein the pixel signal reading unit includes current source circuits each of which includes a load element as a current source connected to the pixel signal reading line forming a source follower, and the current source circuit includes a circuit generating electric current according to a slew rate of the pixel signal reading line and replicating electric current corresponding to the above electric current to flow in the current source.

Abstract: There is provided a current mirror that includes at least one bias amplifier configured to adjust a gate line voltage by feeding currents to the gate line to make constant gate-source voltages of a plurality of FETs (Field Effect Transistors), the gate line connecting gates of the FETs each being a load component in the current mirror.

Abstract: An image sensor includes a capacitor, a low-impedance virtual battery, and a boost current source. The capacitor includes one end connected to a vertical signal line and the other end. The low-impedance virtual battery is connected to the other end of the capacitor and configured to detect a current flowing in the capacitor. The boost current source is configured to provide a boost current to the vertical signal line, the boost current being a current corresponding to the current flowing in the capacitor.

Abstract: A solid-state imaging device includes: pixel signal reading lines; a pixel unit in which pixels including photoelectric conversion elements are arranged; and a pixel signal reading unit performing reading of pixel signals from the pixel unit through the pixel signal reading lines, wherein the pixel signal reading unit includes current source circuits each of which includes a load element as a current source connected to the pixel signal reading line forming a source follower, and the current source circuit includes a circuit generating electric current according to a slew rate of the pixel signal reading line and replicating electric current corresponding to the above electric current to flow in the current source.

Abstract: Disclosed herein is a signal processing circuit including: a main path configured to transmit an input signal and output an actual signal; and a negative feedback path configured to feed back the actual signal to an input stage of the main path, wherein the main path includes a main path block that receives an input signal and outputs an actual signal, the negative feedback path includes a negative feedback block that generates a control signal and supplies the control signal to an input part of an input signal of the main path; a replica block that is supplied with a control signal of the negative feedback block to output a pseudo actual signal, and imitates the main path block; and a signal delay block that delays a pseudo actual signal of the replica block by a dead time of a loop.

Abstract: An optical disk reproducing device includes: a signal reproducing section configured to read and decode information recorded on an optical disk by an optical pickup unit, and reproduce the information, wherein the signal reproducing section includes a gain controlled amplifier circuit configured to amplify an radio frequency signal generated from a light receiving element, an automatic gain control circuit configured to control a gain of the gain controlled amplifier circuit, and a signal processing section configured to derive a part of an automatic gain control value generated in the automatic gain control circuit, and generate a control signal for adjusting one of an optical system path and a detection system path for controlling the optical pickup unit.

Abstract: A Phase Locked Loop circuit, includes: a main path through which an input signal is propagated, and an actual signal is output; a main feedback path through which the actual signal is fed back to an input stage of the main path; and a local feedback path through which feedback is carried out from a path middle of the main path to a path middle of an input stage side; the main path including a phase detector, a loop filter, and a controlled oscillator, and the local feedback path including a replica portion, a delay portion, a first subtracter, and a second subtracter.

Abstract: A signal apparatus is provided. The signal value holding apparatus including a determining section to determine a magnitude relationship between a signal value of an input signal and a signal value of a prescribed feedback signal, a first holding section to hold the signal value determined to be larger by the determining section, a subtracting section to subtract a prescribed value from the signal value held by the first holding section and output a result as the feedback signal, and a second holding section to receive the signal value held by the first holding section and hold the signal value supplied from the first holding section when the signal value of the input signal becomes smaller than the signal value of the feedback signal based on a determination result of the magnitude relationship between the signal values by the determining section.

Abstract: A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.