Patents by Inventor Yuji Imoto

Yuji Imoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357925
    Abstract: A minute transistor is provided. A semiconductor device includes a semiconductor over a substrate, a first conductor and a second conductor over the semiconductor, a first insulator over the first conductor and the second conductor, a second insulator over the semiconductor, a third insulator over the second insulator, and a third conductor over the third insulator. The third insulator is in contact with a side surface of the first insulator. The semiconductor includes a first region where the semiconductor overlaps with a bottom surface of the first conductor, a second region where the semiconductor overlaps with a bottom surface of the second conductor, and a third region where the semiconductor overlaps with a bottom surface of the third conductor. The length between a top surface of the semiconductor and the bottom surface of the third conductor is longer than the length between the first region and the third region.
    Type: Application
    Filed: June 18, 2020
    Publication date: November 12, 2020
    Inventors: Satoshi TORIUMI, Takashi HAMADA, Tetsunori MARUYAMA, Yuki IMOTO, Yuji ASANO, Ryunosuke HONDA, Shunpei YAMAZAKI
  • Publication number: 20200321306
    Abstract: The semiconductor device includes a semiconductor element substrate having an insulation property, and a wire for positioning the semiconductor element with respect to the semiconductor element substrate. The semiconductor element substrate includes a disposition region for disposing the semiconductor element. The wire is provided at least at a part of the periphery of the disposition region.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 8, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takumi SHIGEMOTO, Satoru ISHIKAWA, Yuji IMOTO
  • Patent number: 10770376
    Abstract: A semiconductor chip (2a) is bonded to an upper surface of the conductive substrate (1a). A control terminal (11a) is disposed outside the semiconductor chip (2a) and connected to a control electrode of the semiconductor chip (2a) via a lead (12a). A case (10) surrounds the semiconductor chip (2a). A sealing material (13) seals the semiconductor chip (2a). The lead frame (4) includes a bonded part (4a) joined to the semiconductor chip (2a), and an upright part (4b) embedded in the case (10), extending from the bonded part (4a) to an outer side of the control terminal (11a), and standing upright vertically relative to an upper surface of the semiconductor chip (2a).
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Yuji Imoto, Taishi Sasaki, Tatsuya Kawase
  • Publication number: 20200251425
    Abstract: The object is to provide a technique that can prevent cracks from appearing in an undesirable portion in a resin. A semiconductor device includes an electronic circuit including a semiconductor element, a metal electrode directly connected to the electronic circuit, and an encapsulation resin. The encapsulation resin encapsulates the electronic circuit and the metal electrode. An end portion of the metal electrode on a surface opposite to a surface facing the electronic circuit is acute-shaped, and an end portion of the metal electrode on the surface facing the electronic circuit is arc-shaped or obtuse-shaped.
    Type: Application
    Filed: December 13, 2017
    Publication date: August 6, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yuji IMOTO
  • Patent number: 10727163
    Abstract: A semiconductor device includes a semiconductor element having a front electrode, an electrode plate having an area larger than the front electrode of the semiconductor element in a two-dimensional view and made of aluminum or aluminum alloy, and a metal member having a joint surface joined to the front electrode of the semiconductor element with solder, having an area smaller than the front electrode of the semiconductor element in a two-dimensional view, made of a metal different from the electrode plate, and fastened to the electrode plate to electrically connect the front electrode of the semiconductor element to the electrode plate.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Patent number: 10707141
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Osamu Usui, Yuji Imoto
  • Patent number: 10693013
    Abstract: A minute transistor with low parasitic capacitance, high frequency characteristics, favorable electrical characteristics, stable electrical characteristics, and low off-state current is provided. A semiconductor device includes a semiconductor over a substrate, a source and a drain over the semiconductor, a first insulator over the source and the drain, a second insulator over the semiconductor, a third insulator in contact with a side surface of the first insulator and over the second insulator, and a gate over the third insulator. The semiconductor includes a first region overlapping with the source, a second region overlapping with the drain, and a third region overlapping with the gate. The length between a top surface of the third region of the semiconductor and a bottom surface of the gate is longer than the length between the first region and the third region.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 23, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Takashi Hamada, Tetsunori Maruyama, Yuki Imoto, Yuji Asano, Ryunosuke Honda, Shunpei Yamazaki
  • Publication number: 20200161646
    Abstract: A nickel-hydrogen secondary battery includes an electrode group comprising a separator, a positive electrode, and a negative electrode, and the positive electrode contains a positive electrode active material including a base particle comprising a nickel hydroxide particle containing Mn in solid solution and a conductive layer comprising a Co compound and covering the surface of the base particle, wherein the X-ray absorption edge energy of Mn detected within 6500 to 6600 eV by measurement with an XAFS method is 6548 eV or higher.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Inventors: Takeshi Ito, Yuzo Imoto, Masaru Kihara, Takayuki Yano, Shigekazu Yasuoka, Shuuichi Doi, Takashi Yamazaki, Yuji Kataoka
  • Patent number: 10658324
    Abstract: A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 ?m or more.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Murata, Yuji Imoto
  • Publication number: 20200098701
    Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).
    Type: Application
    Filed: February 9, 2017
    Publication date: March 26, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki HARADA, Naoki YOSHIMATSU, Osamu USUI, Yuji IMOTO, Yuki YOSHIOKA
  • Publication number: 20200083129
    Abstract: An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.
    Type: Application
    Filed: April 27, 2018
    Publication date: March 12, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji FUJINO, Yuji IMOTO, Shohei OGAWA, Mikio ISHIHARA
  • Publication number: 20200028017
    Abstract: A light-receiving element includes an on-chip lens; an interconnection layer; and a semiconductor layer that is disposed between the on-chip lens and the interconnection layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit that is disposed at the periphery of the first voltage application unit, a second charge detection unit that is disposed at the periphery of the second voltage application unit, and a charge discharge region that is provided on an outer side of an effective pixel region. For example, the present technology is applicable to a light-receiving element that generates distance information in a ToF method, or the like.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 23, 2020
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: TSUTOMU IMOTO, YUJI ISOGAI, TAKUYA MARUYAMA, TAKURO MURASE, RYOTA WATANABE, TAKESHI YAMAZAKI
  • Patent number: 10504820
    Abstract: A plurality of semiconductor devices (4a-4f, 5a-5f) are provided on an upper surface of the conductive base plate (1) via an insulating substrate (2) and a conductive pattern (3a-3d). A plurality of fins (6) are provided on a lower surface of the conductive base plate (1). A heat dissipating base plate (7) is provided to tips of the plurality of fins (6). A cooler (8) having an inflow port (9a) and an outflow port (9b) in a bottom surface surrounds the plurality of fins (6) and the heat dissipating base plate (7). A partition (10) separates a space surrounded by the cooler (8) and the heat dissipating base plate (7) into an inflow-side space (11a) connected to the inflow port (9a) and an outflow-side space (11b) connected to the outflow port (9b). A first slit (12a) is provided in a central portion of the heat dissipating base plate (7). Second and third slits (12b,12c) are respectively provided on both sides of the heat dissipating base plate (7) along a direction from an inflow side to an outflow side.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: December 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuya Kawase, Yosuke Nakata, Yuji Imoto, Osamu Usui
  • Publication number: 20190295924
    Abstract: A plurality of semiconductor devices (4a-4f, 5a-5f) are provided on an upper surface of the conductive base plate (1) via an insulating substrate (2) and a conductive pattern (3a-3d). A plurality of fins (6) are provided on a lower surface of the conductive base plate (1). A heat dissipating base plate (7) is provided to tips of the plurality of fins (6). A cooler (8) having an inflow port (9a) and an outflow port (9b) in a bottom surface surrounds the plurality of fins (6) and the heat dissipating base plate (7). A partition (10) separates a space surrounded by the cooler (8) and the heat dissipating base plate (7) into an inflow-side space (11a) connected to the inflow port (9a) and an outflow-side space (11b) connected to the outflow port (9b). A first slit (12a) is provided in a central portion of the heat dissipating base plate (7). Second and third slits (12b,12c) are respectively provided on both sides of the heat dissipating base plate (7) along a direction from an inflow side to an outflow side.
    Type: Application
    Filed: October 21, 2016
    Publication date: September 26, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tatsuya KAWASE, Yosuke NAKATA, Yuji IMOTO, Osamu USUI
  • Publication number: 20190295932
    Abstract: A semiconductor chip (2a) is bonded to an upper surface of the conductive substrate (1a). A control terminal (11a) is disposed outside the semiconductor chip (2a) and connected to a control electrode of the semiconductor chip (2a) via a lead (12a). A case (10) surrounds the semiconductor chip (2a). A sealing material (13) seals the semiconductor chip (2a). The lead frame (4) includes a bonded part (4a) joined to the semiconductor chip (2a), and an upright part (4b) embedded in the case (10), extending from the bonded part (4a) to an outer side of the control terminal (11a), and standing upright vertically relative to an upper surface of the semiconductor chip (2a).
    Type: Application
    Filed: November 11, 2016
    Publication date: September 26, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yosuke NAKATA, Yuji IMOTO, Taishi SASAKI, Tatsuya KAWASE
  • Publication number: 20190267297
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Application
    Filed: October 24, 2016
    Publication date: August 29, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Naoki YOSHIMATSU, Osamu USUI, Yuji IMOTO
  • Patent number: 10388589
    Abstract: The object is to provide a technology capable of enhancing a cooling performance of a semiconductor device. The semiconductor device includes a fin portion including a plurality of projecting portions that are connected to a lower surface of a heat-transfer base plate, a cooling member covering the fin portion and being connected to an inlet through which coolant to flow toward the fin portion flows in and an outlet through which coolant flowing from the fin portion flows out, and a header being a water storage chamber that is provided between the inlet and the fin portion and is partitioned from the fin portion so as to be capable of allowing coolant to flow through from the inlet to the fin portion.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 20, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuya Kawase, Mikio Ishihara, Noboru Miyamoto, Yosuke Nakata, Yuji Imoto
  • Publication number: 20190189537
    Abstract: A semiconductor device includes a semiconductor element having a front electrode, an electrode plate having an area larger than the front electrode of the semiconductor element in a two-dimensional view and made of aluminum or aluminum alloy, and a metal member having a joint surface joined to the front electrode of the semiconductor element with solder, having an area smaller than the front electrode of the semiconductor element in a two-dimensional view, made of a metal different from the electrode plate, and fastened to the electrode plate to electrically connect the front electrode of the semiconductor element to the electrode plate.
    Type: Application
    Filed: July 25, 2017
    Publication date: June 20, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Patent number: 10211122
    Abstract: An object of the present invention is to provide a semiconductor module with high heat dissipation at a low cost. A semiconductor module according to the present invention includes: a case having a hollow portion; a base board made of an aluminum alloy having a first portion corresponding to the hollow portion of the case, and a second portion corresponding to a main body portion of the case, the base board being attached to a bottom face of the case via the second portion; a ceramic insulating substrate disposed on the first portion of the base board; a wiring pattern disposed on the ceramic insulating substrate; semiconductor elements disposed on the wiring pattern; metal wiring boards connected to the semiconductor elements; and a sealing resin that seals the hollow portion of the case.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 19, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hajime Kato, Mikio Ishihara, Yuji Imoto
  • Patent number: 10204886
    Abstract: A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: February 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Yoshida, Yuji Imoto, Hidetoshi Ishibashi, Daisuke Murata, Kenta Nakahara, Seiji Oka, Junji Fujino, Nobuhiro Asaji