Patents by Inventor Yuji Imoto

Yuji Imoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230122091
    Abstract: A glass structure includes: a glass substrate that includes a thick portion and a thin portion thinner than the thick portion; and a filler that covers a step surface formed by difference in height between the thick portion and the thin portion. A refractive index difference at a wavelength of 555 nm between the glass substrate and the filler is 0.008 or less in an absolute value. A refractive index difference at a wavelength of 507 nm between the glass substrate and the filler is 0.008 or less in an absolute value.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: AGC Inc.
    Inventors: Izuru KASHIMA, Yuji IMOTO
  • Publication number: 20220306528
    Abstract: The present invention relates to a chemically strengthened glass including alkali metal ions, having a thickness of 0.20 mm or smaller, and having a pair of major surfaces that are opposed to each other and have been subjected to a chemically strengthening treatment, in which at least one of the pair of major surfaces has a core roughness depth Sk of 0.90 nm or smaller and a mean summit curvature Ssc of 13.0×10?4/nm or smaller.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 29, 2022
    Applicant: AGC INC.
    Inventors: Yuji IMOTO, Yusuke FUJIWARA
  • Patent number: 11450592
    Abstract: A semiconductor device according to the disclosure includes a first semiconductor chip, a second semiconductor chip, a first metal plate provided on an upper surface of the first semiconductor chip, a second metal plate provided on an upper surface of the second semiconductor chip and a sealing resin covering the first semiconductor chip, the second semiconductor chip, the first metal plate and the second metal plate, wherein a groove is formed in the sealing resin, the groove extending downwards from an upper surface of the sealing resin, the first metal plate includes, at an end facing the second metal plate, a first exposed portion exposed from a side face of the sealing resin forming the groove, and the second metal plate includes, at an end facing the first metal plate, a second exposed portion exposed from a side face of the sealing resin forming the groove.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 20, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroya Sannai, Kei Hayashi, Yosuke Nakata, Tatsuya Kawase, Yuji Imoto
  • Publication number: 20220285254
    Abstract: A semiconductor device includes a semiconductor element and a lead part. The semiconductor element is mounted on a circuit pattern provided on an insulating substrate. The lead part has a plate shape and is bonded to the semiconductor element with a first bonding material interposed therebetween. The lead part includes a lead body and a bonding component. The lead body includes an opening part provided corresponding to a mounting position of the semiconductor element. The bonding component is provided in the opening part and on the semiconductor element. The bonding component is bonded at a lower surface thereof to the semiconductor element by the first bonding material and bonded at an outer peripheral part thereof to an inner periphery of the opening part by a second bonding material.
    Type: Application
    Filed: October 17, 2019
    Publication date: September 8, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Atsushi MAEDA, Tatsuya KAWASE, Yuji IMOTO
  • Publication number: 20220278004
    Abstract: An insulating substrate (2) is provided on a base plate (1). A semiconductor device (6-9) is provided on the insulating substrate (2). A case (10) is arranged to surround the insulating substrate and the semiconductor device and bonded to the base plate (1) with an adhesive (11). A sealant (22) seals the insulating substrate and the semiconductor device in the case (10). A groove (23) is provided on a lower surface of the case (10) opposing an upper surface peripheral portion of the base plate (1). A bottom surface of the groove (23) has a protruding part (24) protruding toward the base plate (1). The protruding part (24) includes a vertex (25) and gradients (26,27) respectively provided on an inner side and on an outer side of the case (10) with the vertex (25) sandwiched therebetween. The adhesive (11) contacts the vertex (25) and is housed in the groove (23).
    Type: Application
    Filed: November 27, 2019
    Publication date: September 1, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroya SANNAI, Seiichiro INOKUCHI, Yuji IMOTO, Arata IIZUKA
  • Patent number: 11257768
    Abstract: The object is to provide a technique that can prevent cracks from appearing in an undesirable portion in a resin. A semiconductor device includes an electronic circuit including a semiconductor element, a metal electrode directly connected to the electronic circuit, and an encapsulation resin. The encapsulation resin encapsulates the electronic circuit and the metal electrode. An end portion of the metal electrode on a surface opposite to a surface facing the electronic circuit is acute-shaped, and an end portion of the metal electrode on the surface facing the electronic circuit is arc-shaped or obtuse-shaped.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: February 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Imoto
  • Patent number: 11239123
    Abstract: A base plate (1) includes a fixed surface and a radiating surface which is a surface opposite to the fixed surface. An insulating substrate (3) is bonded to the fixed surface of the base plate (1). Conductive patterns (4,5) are provided on the insulating substrate (3). Semiconductor chips (7,8) are bonded to the conductive pattern (4). An Al wire (12) connects top surfaces of the semiconductor chip (8) to the conductive pattern (5). The insulating substrate (3), the conductive patterns (4 ,5), the semiconductor chips (7 to 10) and the Al wires (11 to 13) are sealed with resin (16). The base plate (1) includes a metal part (19) and a reinforcing member (20) provided in the metal part (19). A Young's modulus of the reinforcing member (20) is higher than a Youngs modulus of the metal part (19).
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: February 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuya Kawase, Noboru Miyamoto, Mikio Ishihara, Junji Fujino, Yuji Imoto, Naoki Yoshimatsu
  • Patent number: 11145616
    Abstract: The semiconductor device includes a semiconductor element substrate having an insulation property, and a wire for positioning the semiconductor element with respect to the semiconductor element substrate. The semiconductor element substrate includes a disposition region for disposing the semiconductor element. The wire is provided at least at a part of the periphery of the disposition region.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: October 12, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takumi Shigemoto, Satoru Ishikawa, Yuji Imoto
  • Patent number: 11101225
    Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: August 24, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Harada, Naoki Yoshimatsu, Osamu Usui, Yuji Imoto, Yuki Yoshioka
  • Publication number: 20210225740
    Abstract: A semiconductor device according to the disclosure includes a first semiconductor chip, a second semiconductor chip, a first metal plate provided on an upper surface of the first semiconductor chip, a second metal plate provided on an upper surface of the second semiconductor chip and a sealing resin covering the first semiconductor chip, the second semiconductor chip, the first metal plate and the second metal plate, wherein a groove is formed in the sealing resin, the groove extending downwards from an upper surface of the sealing resin, the first metal plate includes, at an end facing the second metal plate, a first exposed portion exposed from a side face of the sealing resin forming the groove, and the second metal plate includes, at an end facing the first metal plate, a second exposed portion exposed from a side face of the sealing resin forming the groove.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 22, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroya SANNAI, Kei HAYASHI, Yosuke NAKATA, Tatsuya KAWASE, Yuji IMOTO
  • Patent number: 10978366
    Abstract: An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Publication number: 20200321306
    Abstract: The semiconductor device includes a semiconductor element substrate having an insulation property, and a wire for positioning the semiconductor element with respect to the semiconductor element substrate. The semiconductor element substrate includes a disposition region for disposing the semiconductor element. The wire is provided at least at a part of the periphery of the disposition region.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 8, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takumi SHIGEMOTO, Satoru ISHIKAWA, Yuji IMOTO
  • Patent number: 10770376
    Abstract: A semiconductor chip (2a) is bonded to an upper surface of the conductive substrate (1a). A control terminal (11a) is disposed outside the semiconductor chip (2a) and connected to a control electrode of the semiconductor chip (2a) via a lead (12a). A case (10) surrounds the semiconductor chip (2a). A sealing material (13) seals the semiconductor chip (2a). The lead frame (4) includes a bonded part (4a) joined to the semiconductor chip (2a), and an upright part (4b) embedded in the case (10), extending from the bonded part (4a) to an outer side of the control terminal (11a), and standing upright vertically relative to an upper surface of the semiconductor chip (2a).
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Yuji Imoto, Taishi Sasaki, Tatsuya Kawase
  • Publication number: 20200251425
    Abstract: The object is to provide a technique that can prevent cracks from appearing in an undesirable portion in a resin. A semiconductor device includes an electronic circuit including a semiconductor element, a metal electrode directly connected to the electronic circuit, and an encapsulation resin. The encapsulation resin encapsulates the electronic circuit and the metal electrode. An end portion of the metal electrode on a surface opposite to a surface facing the electronic circuit is acute-shaped, and an end portion of the metal electrode on the surface facing the electronic circuit is arc-shaped or obtuse-shaped.
    Type: Application
    Filed: December 13, 2017
    Publication date: August 6, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Yuji IMOTO
  • Patent number: 10727163
    Abstract: A semiconductor device includes a semiconductor element having a front electrode, an electrode plate having an area larger than the front electrode of the semiconductor element in a two-dimensional view and made of aluminum or aluminum alloy, and a metal member having a joint surface joined to the front electrode of the semiconductor element with solder, having an area smaller than the front electrode of the semiconductor element in a two-dimensional view, made of a metal different from the electrode plate, and fastened to the electrode plate to electrically connect the front electrode of the semiconductor element to the electrode plate.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji Fujino, Yuji Imoto, Shohei Ogawa, Mikio Ishihara
  • Patent number: 10707141
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Osamu Usui, Yuji Imoto
  • Patent number: 10658324
    Abstract: A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 ?m or more.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Murata, Yuji Imoto
  • Publication number: 20200098701
    Abstract: A semiconductor chip (6) is disposed on the insulation substrate (2). A lead frame (8) is bonded to an upper surface of the semiconductor chip (6). A sealing resin (12) covers the semiconductor chip (6), the insulation substrate (2), and the lead frame (8). A stress mitigation resin (13) having a lower elastic modulus than that of the sealing resin (12) is partially applied to an end of the lead frame (8).
    Type: Application
    Filed: February 9, 2017
    Publication date: March 26, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroyuki HARADA, Naoki YOSHIMATSU, Osamu USUI, Yuji IMOTO, Yuki YOSHIOKA
  • Publication number: 20200083129
    Abstract: An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.
    Type: Application
    Filed: April 27, 2018
    Publication date: March 12, 2020
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junji FUJINO, Yuji IMOTO, Shohei OGAWA, Mikio ISHIHARA
  • Patent number: 10504820
    Abstract: A plurality of semiconductor devices (4a-4f, 5a-5f) are provided on an upper surface of the conductive base plate (1) via an insulating substrate (2) and a conductive pattern (3a-3d). A plurality of fins (6) are provided on a lower surface of the conductive base plate (1). A heat dissipating base plate (7) is provided to tips of the plurality of fins (6). A cooler (8) having an inflow port (9a) and an outflow port (9b) in a bottom surface surrounds the plurality of fins (6) and the heat dissipating base plate (7). A partition (10) separates a space surrounded by the cooler (8) and the heat dissipating base plate (7) into an inflow-side space (11a) connected to the inflow port (9a) and an outflow-side space (11b) connected to the outflow port (9b). A first slit (12a) is provided in a central portion of the heat dissipating base plate (7). Second and third slits (12b,12c) are respectively provided on both sides of the heat dissipating base plate (7) along a direction from an inflow side to an outflow side.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: December 10, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuya Kawase, Yosuke Nakata, Yuji Imoto, Osamu Usui