Abstract: A sampling frequency converter includes an oversampling circuit for oversampling an input sample train, a Random Access Memory (RAM), a write control circuit for writing oversampled data in the RAM with a clock synchronized with the oversampled data, a sampling frequency ratio measuring circuit for measuring a frequency ratio of a sampling frequency of the input sample train and a sampling frequency of an output sample train, a read control circuit for reading from the RAM the oversampled data used for obtaining interpolation data at two points before and after an output sample value which realizes the measured sampling frequency ratio by a polynomial interpolation, a polynomial interpolation circuit for obtaining the interpolation data at the two points by the polynomial interpolation on the basis of the oversampled data read from the RAM by the read control circuit, and a linear interpolation circuit for linear-interpolating between the polynomial interpolation data at the two points and thereby obtaining t

Abstract: In a method for synchronizing recording and reproducing devices including a master device and a slave device, during a recording mode and in a state where reference clock of the slave device is synchronized with reference clock of the master device, position information which is synchronized with the reference clock of the master device is recorded commonly in both the master and slave devices and information to be recorded is simultaneously recorded in both the master and slave devices. During a playback mode, the master device and the slave device reproduce the position information respectively at their own reference clocks and cause internal counters provided in the respective devices to perform counting at their own reference clocks and to be reset at a predetermined period of the position information reproduced in the respective devices.

Abstract: A signal processing large scale integrated circuit for carrying out convolution calculations includes multiple delay stages serially connected to thereby form an input data path for a first input signal, a first calculation circuit wherein predetermined calculations are carried out using the output of each of the above mentioned delay stages and a second calculation circuit connected to a convolution path wherein predetermined calculations are carried out using the output of the above mentioned first calculation circuit and a second input signal output from another large scale integrated circuit. The problem of a prolonged delay when multiple LSI circuits are cascade-connected together is eliminated by outputting the first output signal from an intermediate delay element and supplying it as the input to the next stage large scale integrated circuit.

Abstract: An analog-to-digital converting unit comprises an analog level varying circuit having a plurality of gains and varying a magnitude of an analog input signal for producing a plurality of analog output signals different in magnitude from one another with the respective gains, a plurality of analog-to-digital converting circuits respectively supplied with the analog output signals and producing a plurality of digital code signals, respectively, a controlling circuit supplied with two of the digital code signals and calculating a difference therebetween for producing a first control signal indicative of varying one of the digital code signals in value so as to be equal in value to the other digital code signal, a calculating circuit responsive to the first control signal and causing one of the digital code signals to be varied in value for producing a candidate of a digital output signal, and an output circuit coupled to one of the analog-to-digital converting circuits and to the calculating circuit and supplying

Abstract: A reverberation imparting device comprises a delay memory storing input signal data at a predetermined sampling period and producing a delay signal corresponding to time interval between writing of the input signal data and reading thereof, a plurality of address each adding delay signals read out from the delay memory, and an output section for delivering out an output of each of the adders as a reverberation signal. The delay signals are divided into groups and processed on the group basis. This simplifies the construction of the device and facilitates setting and changing of the reverberation characteristics.

Abstract: A reverberation imparting device comprises a prememory storing an input signal, a level detection circuit responsive to data stored in the prememory for detecting presence or absence of the input signal, a data memory storing a delayed input signal delivered out of the prememory, a fixed type convolution operation circuit for producing a reverberation signal with respect to the data stored in the prememory by using an initial portion of parameters of a reflected sound, an adaptive type convolution operation circuit for producing a reverberation signal with respect to data stored in the data memory by using a plurality of parameters of more significant bits among the remaining portion of the parameters of the reflected sound, and an adder for adding outputs of the fixed type and adaptive type convolution circuits and delivering out the result of addition as a reverberation signal.