Patents by Inventor Yuji Kayashima

Yuji Kayashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347552
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
  • Publication number: 20190189601
    Abstract: The characteristics of an electronic device can be improved. The electronic device includes a first redistribution layer formed over an upper surface US of a sealing body, and a second redistribution layer formed below a bottom surface of the sealing body. The thickness of the second redistribution layer is smaller than the thickness of the first redistribution layer.
    Type: Application
    Filed: September 28, 2018
    Publication date: June 20, 2019
    Inventor: Yuji Kayashima
  • Patent number: 10325841
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Katsushi Terajima, Keita Tsuchiya, Yoshiaki Sato, Hiroyuki Uchida, Yuji Kayashima, Shuuichi Kariyazaki, Shinji Baba
  • Patent number: 10297547
    Abstract: A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuji Kayashima, Tomohisa Sekiguchi
  • Publication number: 20180374788
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Application
    Filed: February 10, 2016
    Publication date: December 27, 2018
    Inventors: Kazuyuki NAKAGAWA, Katsushi TERAJIMA, Keita TSUCHIYA, Yoshiaki SATO, Hiroyuki UCHIDA, Yuji KAYASHIMA, Shuuichi KARIYAZAKI, Shinji BABA
  • Publication number: 20180247893
    Abstract: A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.
    Type: Application
    Filed: January 3, 2018
    Publication date: August 30, 2018
    Inventors: Yuji Kayashima, Tomohisa Sekiguchi
  • Publication number: 20180151460
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Application
    Filed: January 25, 2018
    Publication date: May 31, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Ryuichi OIKAWA, Toshihiko OCHIAI, Shuuichi KARIYAZAKI, Yuji KAYASHIMA, Tsuyoshi KIDA
  • Patent number: 9917026
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
  • Publication number: 20170213776
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Application
    Filed: December 24, 2014
    Publication date: July 27, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Ryuichi OIKAWA, Toshihiko OCHIAI, Shuuichi KARIYAZAKI, Yuji KAYASHIMA, Tsuyoshi KIDA
  • Patent number: 8043953
    Abstract: A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideya Murai, Yuji Kayashima, Takehiko Maeda, Shintaro Yamamichi, Takuo Funaya
  • Publication number: 20090294951
    Abstract: A semiconductor device that can be readily manufactured, can include a large number of pads, and can be thin, and a method for manufacturing the same are provided. The semiconductor device is characterized in that the semiconductor device includes an LSI chip, an insulating layer provided on the LSI chip and made of a nonphotosensitive resin, the insulating layer including a via hole in the position corresponding to an externally connected pad, and a wiring layer extending along the insulating layer through the via hole to the externally connected pad, and at least part of the via hole is formed by irradiating the insulating layer with laser light.
    Type: Application
    Filed: January 15, 2008
    Publication date: December 3, 2009
    Applicant: NEC CORPORATION
    Inventors: Hideya Murai, Yuji Kayashima, Takehiko Maeda, Shintaro Yamamichi, Takuo Funaya
  • Patent number: 6414336
    Abstract: In a method for manufacturing a semiconductor device, probe pads are formed simultaneously with formation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device in accordance with characteristics of the semiconductor device obtained by the test operation.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: July 2, 2002
    Assignee: NEC Corporation
    Inventor: Yuji Kayashima
  • Publication number: 20010049151
    Abstract: In a method for manufacturing a semiconductor device, probe pads are formed simultaneously with formation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device ill accordance with characteristics of the semiconductor device obtained by the test operation.
    Type: Application
    Filed: July 11, 2001
    Publication date: December 6, 2001
    Inventor: Yuji Kayashima
  • Patent number: 6309898
    Abstract: In a method for manufacturing a semiconductor device, probe pads are formed simultaneously with formation of an intermediate conductive layer, and a test operation is performed upon the semiconductor device by placing probes on the probe pads. Then, post-stage processes are performed upon the semiconductor device in accordance with characteristics of the semiconductor device obtained by the test operation.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: October 30, 2001
    Assignee: NEC Corporation
    Inventor: Yuji Kayashima