Abstract: A memory cell is provided with an N-channel MOS transistor as a transfer gate, a capacitor for accumulating charges corresponding to stored information, and a charge compensating circuit. Charge compensating circuit is a bi-stable circuit formed of two stages of inverters and latches a logic level of a node. Load resistors of inverters are constituted of P-channel thin film transistors made of polycrystalline polysilicon which can be formed on upper layers of N-channel MOS transistors as bulk transistors. As a result, a semiconductor memory device can realize a higher packing density and a larger capacity close to those of a DRAM without requiring refresh operations.

Abstract: Two memory cells are provided for storage data of one bit, and stores data inverted from each other. Memory cells include charge compensating circuits, respectively, each being formed of an inverter, and charge compensating circuits include P-channel TFTs, respectively, which can be formed on bulk transistors. Charge compensating circuits are cross coupled, and latch data stored in memory cells. As a result, a semiconductor memory device can realize a higher packing density and a larger capacity without requiring refresh operations.

Abstract: A semiconductor memory device having a redundant circuit includes a substitution memory cell circuit (2) having a spare memory cell, and a switching control circuit (1) for controllably substituting the spare memory cell for an individual defective memory cell whenever the row and column addresses of the defective cell are addressed. The spare memory cell (21) is constituted by a flip-flop and is capable of driving a read data bus (5) without amplification. Hence, it is possible to prevent the delay in accessing from being caused by use of the redundant circuit, as well as preventing excessive density and complexity in the masking pattern for this semiconductor memory. In one aspect of the invention the redundant circuit includes a spare memory cell that has inverters for amplification.

Abstract: A static type semiconductor memory device is provided with a power circuit for a disturb test, in which MOS transistors constituting a memory cell are examined for an abnormal threshold voltage. A P-channel MOS transistor is provided between a power supply, and the memory cells. The P-channel MOS transistor is rendered conductive in the normal mode, allowing the voltage to the memory cells as under normal circumstances. In addition, between the power supply and the memory cells, there is provided a series-connection of a diode-connected N-channel MOS transistor and a P-channel MOS transistor. In the disturb test, this P-channel MOS transistor is rendered conductive. As a result, the supply voltage reduced by the N-channel MOS transistor, or a voltage lower than the supply voltage by the threshold voltage of this N-channel MOS transistor is supplied to the memory cells.

Abstract: An input buffer for semiconductor integrated circuits has a resistor (16), capacitor (17) and a logical gate comprising transistors (11, 12, 13) connected in series between a supply line (61) and a ground line (62). The resistor (16) reduces the through current which flows toward the ground (Vss) when the logical gate switches. In a high speed operation, the capacitor (17) supplies current to the logical gate so that any delay which may possibly be caused by the provision of the resistor (16) can be prevented.

Abstract: An input buffer circuit of a MOS memory device includes an input terminal for receiving an address signal, complementary output terminals, and an inverter circuit which propagates the address signal from the input terminal to the complementary output terminals, to provide the complementary output terminals with an address signal and an inverted address signal. A transition of the address signal is detected as it is propagated through the inverter circuit, and the potentials of the complementary output terminals are equalized before the transition is propagated to the complementary output terminals.

Abstract: A MOS-type memory circuit comprising a terminal end potential feeder circuit which applies a voltage of certain level between a supply voltage and a ground potential to terminal ends of word lines when memory addresses change-over.