Patents by Inventor Yuji Maruyama
Yuji Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170124403Abstract: Even if a problem has occurred with respect to a multimedia micro-computer that generates a composite image including guiding lines, while a gearshift of a vehicle is in reverse, a reset process is not performed for the multimedia micro-computer. The reset process is performed after the gearshift is determined to have moved from reverse.Type: ApplicationFiled: October 13, 2016Publication date: May 4, 2017Applicant: FUJITSU TEN LIMITEDInventors: Kenji TADA, Yuji MARUYAMA, Nobuyuki BATOU
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Publication number: 20170093235Abstract: The motor of the invention includes the resin sealing member which covers a stator and a circuit board. The stator includes a stator core for winding a driving coil through an insulation member, and a terminal pin secured to the insulation member. The insulation member includes a press fitting portion for pressing and securing a portion of the terminal pin on a side of a second direction, whereas a portion of the terminal pin on a side of a first direction is soldered to the circuit board. A stopper portion is formed on a second direction end of the terminal pin. The stopper portion contacts a surface of the press fitting portion in the second direction to prevent the terminal pin from falling off in the first direction.Type: ApplicationFiled: September 29, 2016Publication date: March 30, 2017Applicant: NIDEC SANKYO CORPORATIONInventors: Keishi OTSUBO, Shinichi UTSUMI, Yuji MARUYAMA, Hideo SHIMODAIRA
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Publication number: 20150015070Abstract: An electronic device includes a case; a power source unit including a heat generation unit, the power source unit being configured to be inserted in the case and slidable between a stored state in which the power source unit is stored in the case and an exposed state in which at least the heat generation unit is exposed from the case; a detection unit configured to detect the stored state or the exposed state of the power source unit; and a control unit configured to control a load with respect to the power source unit, according to the stored state or the exposed state detected by the detection unit.Type: ApplicationFiled: October 2, 2014Publication date: January 15, 2015Inventors: Hirotaka YAKAME, Yuji MARUYAMA
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Patent number: 8648617Abstract: According to the following disclosure, disclosed is a semiconductor device including: an internal circuit configured to receive and output a signal current; a current mirror unit outputting a copied current corresponding to the signal current; and a test pad from which the copied current is taken out.Type: GrantFiled: February 7, 2011Date of Patent: February 11, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Yuji Maruyama, Tatsuhiro Mizumasa, Takayuki Nakashiro, Shigeru Gotoh, Takayuki Yano, Susumu Koshinuma, Shunsuke Taniguchi, Yuki Yanagisako
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Patent number: 8159250Abstract: A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.Type: GrantFiled: July 10, 2009Date of Patent: April 17, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Yuji Maruyama, Kazuhiro Tashiro, Kazuhiko Shimabayashi, Shigeru Goto, Takayuki Nakashiro, Susumu Koshinuma, Masayoshi Shirakawa
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Publication number: 20110221466Abstract: According to the following disclosure, disclosed is a semiconductor device including: an internal circuit configured to receive and output a signal current; a current mirror unit outputting a copied current corresponding to the signal current; and a test pad from which the copied current is taken out.Type: ApplicationFiled: February 7, 2011Publication date: September 15, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yuji MARUYAMA, Tatsuhiro Mizumasa, Takayuki Nakashiro, Shigeru Gotoh, Takayuki Yano, Susumu Koshinuma, Shunsuke Taniguchi, Yuki Yanagisako
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Publication number: 20100248878Abstract: The combination of: a) first and second spaced pulleys; b) an endless belt; and c) a belt installation jig having a body with: a pulley pressing part; a belt holding part; and a belt pressing part. The belt installation jig and belt cooperate so that with the belt operatively wrapped against the second pulley and partially operatively wrapped against the first pulley, turning of the first pulley causes the belt to progressively wrap around the first pulley to a fully operatively wrapped state, whereupon further turning of the first pulley situates the belt installation jig for separation from the belt and pulleys.Type: ApplicationFiled: March 22, 2010Publication date: September 30, 2010Inventors: Yuji Maruyama, Hiroki Takechi, Yasuhito Aoki
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Publication number: 20090267630Abstract: A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.Type: ApplicationFiled: July 10, 2009Publication date: October 29, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yuji Maruyama, Kazuhiro Tashiro, Kazuhiko Shimabayashi, Shigeru Goto, Takayuki Nakashiro, Susumu Koshinuma, Masayoshi Shirakawa
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Patent number: 5787191Abstract: A wiring pattern inspection apparatus for inspecting an abnormality of a wiring pattern formed on a printed circuit board, which is equipped with an optical image pickup device for optically illuminating a surface of the printed circuit board including the wiring pattern to photoelectrically convert optical information of the printed circuit board surface due to the optical illumination into a grey level image. This grey level image is converted into a bi-level image which separates the grey level image into the wiring pattern side and a background side of the wiring pattern. Thereafter, the bi-level image is once contracted by a first size and then expanded by a second size so as to eliminate a micro conductive portion left on the printed circuit board or a micro pinhole which can be disregarded in the abnormality inspection, thereby preventing the excessive detection.Type: GrantFiled: June 6, 1995Date of Patent: July 28, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideaki Kawamura, Atsuharu Yamamoto, Yuji Maruyama, Hidehiko Kawakami, Katsuhiro Kondoh, Iwao Ichikawa
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Patent number: 5608816Abstract: Pieces of feature information in a bi-level image such as a width, a branching point and an ending point of a wiring pattern are detected in a design rule checking section according to a micro inspection to find out pieces of feature information departing from a design rule. Also, feature codes in the bi-level image such as a corner of the wiring pattern are detected in a specific shape detecting section according to a macro inspection. The feature information are compared with pieces of referential feature information pertaining to a non-defective wiring pattern in a first comparing and judging section to judge whether the wiring pattern indicated by the feature information is defective or non-defective. The feature codes are compared with referential feature codes pertaining to a non-defective wiring pattern in a second comparing and judging section to judge whether the wiring pattern indicated by the feature codes is defective or non-defective.Type: GrantFiled: September 15, 1994Date of Patent: March 4, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoki Kawahara, Atsuharu Yamamoto, Yuji Maruyama, Hidehiko Kawakami, Hideaki Kawamura
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Patent number: 5459795Abstract: A wiring pattern inspection apparatus for inspecting an abnormality of a wiring pattern formed on a printed circuit board, which is equipped with an optical image pickup device for optically illuminating a surface of the printed circuit board including the wiring pattern to photoelectrically convert optical information of the printed circuit board surface due to the optical illumination into a grey level image. This grey level image is converted into a bi-level image which separates the grey level image into the wiring pattern side and a background side of the wiring pattern. Thereafter, the bi-level image is once contracted by a first size and then expanded by a second size so as to eliminate a micro conductive portion left on the printed circuit board or a micro pinhole which can be disregarded in the abnormality inspection, thereby preventing the excessive detection.Type: GrantFiled: March 29, 1994Date of Patent: October 17, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hideaki Kawamura, Atsuharu Yamamoto, Yuji Maruyama, Hidehiko Kawakami, Katsuhiro Kondoh, Iwao Ichikawa
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Patent number: 5272763Abstract: An inspection apparatus for inspecting a wiring pattern on a printed board by illuminating the printed board with light to photoelectrically convert light reflected from the printed board into an optical grey level image corresponding to the wiring pattern thereon, the grey level image being converted into a bi-level image. The inspection apparatus includes a thinning circuit to perform a thinning process for removing the bi-level image by one picture element from the background side of the wiring pattern, the thinning process being repeatedly performed predetermined times with respect to all of picture elements of the wiring pattern to output the number of repetitions of the thinning process and further to output a skeleton image. Also included is a distance image converter to output a distance conversion image where the number of repetitions is given as a distance value from the background of the wiring pattern.Type: GrantFiled: August 28, 1992Date of Patent: December 21, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuji Maruyama, Atsuharu Yamamoto, Hidemi Takahashi, Hidehiko Kawakami
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Patent number: 5214712Abstract: A pattern inspection system for inspecting a pattern of a land for a through-hole formed in a printed board. In the system there are included a first illumination device for optically illuminating the printed board, a second illumination device for illuminating the printed board with light modulated at a predetermined period and an image pickup responsive to reflection light and transmission light from the printed board due to the first and second illumination devices to photoelectrically convert the printed board into a gray level image. The gray level image is converted into a bi-level image by a bi-level conversion device and then converted into an edge image by an edge detecting device. The edge image is expanded and contracted by predetermined amounts so as to obtain a through-hole image corresponding to the through-hole. A defect detecting device detects a defect of the pattern of the printed board on the basis of the through-hole image and the bi-level image from the bi-level conversion device.Type: GrantFiled: September 10, 1991Date of Patent: May 25, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Atsuharu Yamamoto, Yuji Maruyama, Hidehiko Kawakami, Hideaki Kawamura, Masaaki Nakashima, Hidemi Takahashi
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Patent number: 5200799Abstract: A system for inspecting a condition of parts packaged on a printed-circuit board. The inspection system includes a position detecting device to receive scattered light due to illumination of the printed-circuit board with a laser beam and convert the received scattered light into a position signal. This position signal is used for obtaining luminance data and at least two height data of the parts on the printed-circuit board. Proper height data of the parts is determined on the basis of the difference between the two height data. The inspection system determines the package condition by comparing the final height data with a predetermined reference data.Type: GrantFiled: September 11, 1990Date of Patent: April 6, 1993Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuji Maruyama, Yukifumi Tsuda, Kazutoshi Ikegaya, Kunio Sannomiya, Hiroto Toba, Takumi Seto
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Patent number: 5103105Abstract: A beam of light is applied to a surface of a circuit board provided with at least one solder portion. The light beam scans the surface of the circuit board. Height data are derived from a portion of the light beam which is scattered at the surface of the circuit board. The height data represent a height of a currently-scanned point of the surface of the circuit board. The height data are accumulatively added for the solder portion. A variation in the height data is calculated. The accumulative addition of the height data is executed and suspended in response to the calculated variation in the height data. A decision is made as to whether the solder portion is acceptable or unacceptable on the basis of a result of the accumulative addition.Type: GrantFiled: October 24, 1990Date of Patent: April 7, 1992Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazutoshi Ikegaya, Yuji Maruyama, Yukifumi Tsuda, Kunio Sannomiya, Hiroto Toba
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Patent number: 5027418Abstract: A printed-circuit board inspection apparatus for checking the condition of each circuit component mounted by soldering on a printed-circuit board is disclosed in which a luminance signal obtained from the reflected light scattering from the printed-circuit board being illuminated is converted through a given threshold level to binary signals, then the binary signals and mask data are processed to calculate the ratio of an area represented by the number of binary "1" signals to an area represented by the number of binary "0" signals, and the soldering condition of the component is judged based on the area ratio. With this arrangement, the inspection is not negatively influenced by the misalignment of the component with a mating soldering land, is capable of judging the amount of solder, and can be performed automatically and efficiently.Type: GrantFiled: February 12, 1990Date of Patent: June 25, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazutoshi Ikegaya, Yuji Maruyama, Kunjo Sannomiya, Yukifumi Tsuda, Hiroto Toba
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Patent number: 4983827Abstract: A linescan apparatus for detecting salient pattern on a surface of a product comprises: a laser light source for continuously emitting a laser beam; a polygon mirror for reflecting the laser beam; a drive for rotating the polygon mirror to scan said laser beam; an f.theta. lens arranged such that the linescan laser beam strikes against the plane perpendicularly; a carrying device for moving the product in the direction substantially perpendicular to the plane; a mirror for reflecting the linescan laser beam reflected at a surface of the product to direct the linescan laser beam to the polygon mirror through the f.theta. lens, the mirror being positioned apart from the second plane; and a beam position detector for detecting unidimensional position of a spot mede by the linescan laser beam projected thereon from the mirror via the polygon mirror. This linescan apparatus provides three-dimensional data of a surface of the product.Type: GrantFiled: October 25, 1989Date of Patent: January 8, 1991Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazutoshi Ikegaya, Kunio Sannomiya, Yukifumi Tsuda, Yuji Maruyama, Nobuhiro Araki, Hiroto Toba
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Patent number: 4924322Abstract: An image signal processing apparatus for converting input signal values representing density levels of successive picture elements of an image to corresponding bi-level signal values, whereby a conversion error for an object picture element is apportioned among a set of unprocessed adjacent picture elements, to update respective values of accumulated error. Each input signal value is compensated, prior to conversion, by a value derived from the total accumulated errors of the object picture element and these adjacent picture elements, while the conversion error is derived by subtracting from the bi-level output value a value obtained by compensating the input signal by the accumulated error for the object picture element.Type: GrantFiled: March 17, 1989Date of Patent: May 8, 1990Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshiharu Kurosawa, Hiroyoshi Tsuchiya, Yuji Maruyama, Katsuo Nakazato
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Patent number: 4891710Abstract: An image signal processing circuit for converting step-gradation density values (I.sub.xy) of successive picture elements to bi-level values (P.sub.xy) for display by a bi-level display device, in which a bi-level error (E.sub.xy) between a bi-level value determined for a picture element and an appropriate density value for the element is apportioned among a set of peripherally adjacent picture elements (A to D) by computing a corresponding set of error apportionment values (G.sub.A to G.sub.D), and in which a difference between the sum total of these apportionment values and the bi-level error is derived, and error apportionment is modified such as to eliminate the effects of this difference. Improved reproduction is thereby attained of image regions which are of uniformly high density or low density.Type: GrantFiled: December 21, 1987Date of Patent: January 2, 1990Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuo Nakazato, Toshiharu Kurosawa, Yuji Maruyama, Kiyoshi Takahashi, Hiroyoshi Tsuchiya
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Patent number: 4890167Abstract: An image signal processing circuit for converting a continuous tone image signal to a bi-level image signal, for producing a spatial gray scale image on a bi-level display device such as a gas plasma display panel. Respective values of apportionment factors (K.sub.A to K.sub.D) used for apportioning a bi-level conversion error of each picture element of the image among a plurality of picuture elements (A to D) positioned peripehrally adjacent thereto are periodically altered, in a periodic or random succession of values, to thereby effectively eliminate the generation of a texture pattern in display regions corresponding to areas of uniform density in the original image.Type: GrantFiled: October 16, 1987Date of Patent: December 26, 1989Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Katsuo Nakazato, Hiroyoshi Tsuchiya, Toshiharu Kurosawa, Yuji Maruyama, Kiyoshi Takahashi