Patents by Inventor Yuji Matsuda

Yuji Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6076932
    Abstract: This invention provides a light absorber which can be used for optical equipment like optical-disk equipment and a liquid crystal display. The light absorber has a layered structure including a light absorbing layer and a transparent layer. The light absorbing layer absorbs a reflected light from the inside of the absorber as well as incident light into the absorber while the transparent layer helps attenuate the reflected light by interference of light. One of the light absorbing layers which is thicker than others may work as a shading layer for the incident light.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: June 20, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinji Uchida, Tsuguhiro Korenaga, Hiroyasu Tsuji, Shougo Nasu, Norimoto Nouchi, Toshio Fukazawa, Toshihiro Kuriyama, Yuji Matsuda
  • Patent number: 6046069
    Abstract: A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Katsuya Ishikawa, Takao Kuroda, Yuji Matsuda, Masahiko Niwayama, Keishi Tachikawa
  • Patent number: 6025210
    Abstract: A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: February 15, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Yuji Matsuda, Masahiko Niwayama
  • Patent number: 5966174
    Abstract: A solid-state imaging apparatus includes a solid-state imaging device and a signal processing circuit. The solid-state imaging device includes: a plurality of photoelectric converting sections provided with color filters having different spectroscopic characteristics, and each converting light incident thereon into a charge and accumulating the charge, and a plurality of vertical charge transfer sections for vertically transferring the charge read from each of the photoelectric converting sections. A plurality of reading operations to read the charges accumulated in the photoelectric converting sections to the plurality of the vertical charge transfer sections are performed within a time duration for scanning an image for one image plane, and the charges read from the photoelectric converting sections are transferred through the vertical charge transfer section separately for each of the reading operations.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: October 12, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasutoshi Yamamoto, Masayuki Yoneyama, Hiroyoshi Komobuchi, Yuji Matsuda, Toshiya Fujii
  • Patent number: 5869854
    Abstract: A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: February 9, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Yuji Matsuda, Masahiko Niwayama
  • Patent number: 5867055
    Abstract: A semiconductor device and a method of inspecting the same are described. The semiconductor device does not need voltage adjustment of an external driver circuit, since it contains a voltage generator to inspect and memorize the best value of voltage by controlling from outside. The voltage generator has a plurality of capacitors whose electrodes of one side are connected to a common node, a potential changing circuit to change the potential to which the other electrodes of these capacitors are connected respectively, and a buffer amplifier whose input power is the voltage generated in the common node. The output power of the buffer amplifier is connected to a semiconductor integrated circuit. The potential changing circuit is provided to change the potential to which the electrode of each capacitor is connected to a source potential or to a ground potential depending on the connection of the fuse connected between the source and each of the capacitors.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: February 2, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Masaji Asaumi, Yuji Matsuda
  • Patent number: 5786607
    Abstract: A solid-state image pick-up device having a structure in which the amount of transferred charges is not reduced in a vertical CCD portion even if a pixel portion is made finer, and a method for manufacturing the solid-state image pick-up device are provided. A first p-type well and a second p-type well are formed on an N (100) silicon substrate. A vertical CCD n.sup.+ layer is formed in the second p-type well 3. Then, impurity ions are implanted into a surface layer of the N (100) silicon substrate including an upper layer portion of the vertical CCD n.sup.+ layer to form a p.sup.- layer. An isolating portion for isolating photodiode portions from the vertical CCD n.sup.+ layer and a read control portion for controlling the read of charges from the photodiode n layer are simultaneously formed on a portion adjacent to the vertical CCD n.sup.+ layer.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: July 28, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Katsuya Ishikawa, Takao Kuroda, Yuji Matsuda, Masahiko Niwayama, Keishi Tachikawa
  • Patent number: 5701011
    Abstract: A radiographic apparatus is provided which is capable of converting an X-ray directly into an electric signal, high in resolution and detection efficiency, and easy to manufacture. On at least one surface of a compound semiconductor substrate for generating an electric charge by X-ray irradiation, a plurality of split electrodes are disposed, and electrodes are disposed on picture elements formed on a CCD corresponding to these split electrodes, and are electrically connected to CdTe as compound semiconductor substrate and the CCD. An electric current issued from the split electrodes is divided, and is partly discharged through grounding wires.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: December 23, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Ohmori, Toshiyoshi Yamamoto, Yuji Matsuda, Yoshihiko Tanji, Takayoshi Yuuzu
  • Patent number: 5572329
    Abstract: An image processing apparatus for recording a read image upon a recording medium. If a reading width of an image reading sensor is wider than a recording width of a recording head, the apparatus controls scanning of the image sensor and the recording head. The recording head comprises uniformly aligned recording elements divided into a plurality of groups. Image data read by the image sensor is stored into a memory, then used for activating the recording elements of the recording head. The apparatus conveys a recording medium by a length corresponding to one recording element group at each scanning of the recording head. If the amount of meaningless data or recorded data of the stored data corresponds to the amount of one scanning of the recording head or more, the image sensor performs the next reading.
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: November 5, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshihiko Otsubo, Yuji Matsuda
  • Patent number: 5432363
    Abstract: Photoelectric converting parts and vertical CCD register parts are formed in a semiconductor substrate. Polysilicon electrodes are formed on the vertical CCD register parts. On the polysilicon electrodes, polysilicon oxide film and dielectric film are deposited. On the polysilicon electrodes, contact windows are formed by mask matching and etching. The contact windows are formed in the first polysilicon electrode and second polysilicon electrode so as to realize four-phase drive of the solid-state image pickup device. Polysilicon film and tungsten silicide film are formed thereon. By etching these films, a first wiring is formed. A second wiring of aluminum film is formed thereon through an interlayer dielectric film. Hence, a high transfer efficiency and a favorable smear noise characteristic are presented at low illumination.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: July 11, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Wataru Kamisaka, Hiroyuki Okada, Yuji Matsuda
  • Patent number: 5302545
    Abstract: A charge-coupled device comprises transfer gate electrodes separated from a substrate by a multilayer insulating film, and gate electrodes of MIS transistors separated from the substrate by a single layer insulating film. The multilayer insulating film comprising at least a lower silicon oxide layer of 10 nm to 200 nm thickness and an upper silicon nitride layer of 10 nm to 100 nm thickness. Since each of the gate insulating films of the MIS transistors is the same layer as the lower silicon oxide layer, there occurs no degradation in the transistor characteristics due to the surface states or the trapping states present within the silicon nitride layer.
    Type: Grant
    Filed: June 7, 1993
    Date of Patent: April 12, 1994
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroyuki Okada, Wataru Kamisaka, Masaji Asaumi, Yuji Matsuda
  • Patent number: 5241198
    Abstract: A charge-coupled device comprises transfer gate electrodes separated from a substrate by a multi-layer insulating film, and gate electrodes of MIS transistors separated from the substrate by a single layer insulating film. The multilayer insulating film comprising at least a lower silicon oxide layer of 10 nm to 200 nm thickness and an upper silicon nitride layer of 10 nm to 100 nm thickness. Since each of the gate insulating films of the MIS transistors is the same layer as the lower silicon oxide layer, there occurs no degradation in the transistor characteristics due to the surface states or the trapping states present within the silicon nitride layer.
    Type: Grant
    Filed: November 25, 1991
    Date of Patent: August 31, 1993
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroyuki Okada, Wataru Kamisaka, Masaji Asaumi, Yuji Matsuda
  • Patent number: 4544989
    Abstract: A substrate for wiring an electrical component in an electrical circuit comprises a base substrate, a first insulating layer of an organic material formed over the base substrate, a wiring member formed on the first insulating layer, coupled to the component, a second insulating layer of an organic material formed over the first insulating layer, and a terminal member on the first insulating layer and appearing from the second insulating layer, connected to the wiring member. A third insulating layer of an organic material may be interposed between the first and the second insulating layers, carrying a second wiring member connected to the first wiring member.
    Type: Grant
    Filed: June 26, 1981
    Date of Patent: October 1, 1985
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shigeo Nakabu, Yuji Matsuda, Hirokazu Yoshida, Masaru Iwasaki, Takashi Nukii, Katunobu Awane