Abstract: An imaging lens unit configured for processing by a solder reflow process, and includes a lens group of one or more lenses; and a lens tube supporting the lens group. The imaging lens unit comprises one or more cationically-cured epoxy resin lenses formed from an cationically-curable epoxy resin material, the lens tube is formed from a thermoplastic resin material having a deflection temperature under load of at least 200° C. The imaging lens unit has a clearance between the lens tube and at least one of the cationically-cured epoxy resin lenses and has lens supporting portions provided at least three locations inside the lens tube that support the at least one cationically-cured epoxy resin lens. The lens unit can be miniaturized. The imaging lens unit also provides excellent optical characteristics without deteriorating the optical characteristics in alignment of the centers of the lens and the diaphragm.

Abstract: The present invention provides an imaging lens unit configured to be processed by the solder reflow process, can be miniaturized, and has sufficient thermal resistance for the reflow temperatures. The imaging lens unit also provides excellent optical characteristics such as transmissivity, a refractive index, and the like without deteriorating the optical characteristics in alignment of the centers of the lens and the diaphragm even after the reflow process, so as to contribute to reduction in the size and an increase in the capabilities. The imaging lens unit is configured to be processed by a solder reflow process, and includes a lens group consisting of one or more lenses; and a lens tube that supports the lens group, wherein the imaging lens unit comprises one or more cationically-cured epoxy resin lenses formed from an cationically-curable epoxy resin material, the lens tube is formed from a thermoplastic resin material having a deflection temperature under load of not lower than 200° C.

Abstract: A substrate and a target are disposed within a vacuum chamber, and an oxygen partial pressure within the vacuum chamber is set to 1×10−5 or less. Under this condition, a spinel ferrite thin film selected from the group consisting of compounds represented by the formula AE1+tFe2−2tTMtO4, where AE represents an alkaline earth metal or an alkali metal, TM represents a transition metal and t falls within a range of between 0.2 and 0.6, and compounds represented by the formula Zn1−xCoxFe2O4, where x falls within a range of between 0.2 and 0.7, is deposited on the substrate by laser beam deposition. The particular method makes it possible to provide a spinel ferrite thin film realizing a spin glass state under temperatures around or higher than room temperature and capable of controlling the spin state by light.

Abstract: A semiconductor memory device having a latch signal generating circuit which can latch the read data at a data-read timing corresponding to either of the minimum tCAS and the minimum tCP, that is, in either of the low-potential state and the high-potential state of CASB. The semiconductor memory device has different data-read operation cycles, and comprises a decoder into which an address signal is input; a memory cell array consisting of memory cells; a D-latch circuit for latching data output from one of the memory cells which is selected by the decoder; an output buffer for outputting the data which is output from the D-latch circuit; and a latch signal generating circuit for generating a clock signal used in the D-latch circuit, the generated signal having a data-latch timing which is effective in each data-read operation cycle.

Abstract: An output circuit for a semiconductor memory device includes at least an output transistor and a level conversion circuit. In this case, the level conversion circuit is connected to the output transistor. The output transistor is connected to a ground terminal and an output terminal. In this condition, the level conversion circuit converts an input signal in level and supplies the converted input signal to the output transistor as drive signal. With such a structure, a predetermined booster voltage is given to the level conversion circuit. Consequently, the ground potential appears at the output terminal without an access delay when the output transistor is turned on by the drive signal.