Abstract: To realize a depthwise, pointwise separable convolution (DPSC) operation without increasing a memory size and reduce the number of parameters and the amount of operation in a convolutional layer. This arithmetic operation device includes a first product-sum operator, a second product-sum operator, and a cumulative unit. The first product-sum operator performs a product-sum operation of input data and a first weight. The second product-sum operator is connected to an output portion of the first product-sum operator, and performs a product-sum operation of the output of the first product-sum operator and a second weight. The cumulative unit sequentially adds the output of the second product-sum operator.

Abstract: Test environmental programs are prepared using the following steps: Upon application of H/W specification information containing information on the system architecture, a guidance is displayed based on the H/W specification information and the user is caused to input subsystem definition information. The H/W specification information and the subsystem definition table are related to each other to prepare the specification description of system architecture, which is used together with the simulator in a simulator library to generate test environment programs according to a testee designation. In the application-specific hardware simulator, a hardware simulation model simulating the I/O device behavior is prepared as follows: An internal connection analysis table and a definition table defining various system architectures are prepared from the hardware description information describing the I/O device hardware specification in the specification description language.

Abstract: A method for automatically linking program execution status information during the execution of a program to display the execution status information of the program by a multi-window display having a plurality of sectioned areas for use in the development of the software program.