Abstract: An optical communication apparatus includes a first monitor that monitors a first signal carried on a first polarization and outputs a first monitor value representing a transmission characteristic of the first signal, a second monitor that monitors a second signal carried on a second polarization orthogonal to the first polarization and outputs a second monitor value representing a transmission characteristic of the second signal, and a transmitting circuit that notifies a transmitting source of the first signal and the second signal of the first monitor value and the second monitor value.

Abstract: A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.

Abstract: A transmission apparatus includes: a reception processing unit configured to perform a reception processing on a first signal into which second signals having different rates and including overhead information are hierarchically multiplexed; and a common overhead processing unit configured to process the overhead information included in the first and second signals according to a common rate to hierarchical layers.

Abstract: A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.

Abstract: An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.

Abstract: An ALC processing unit to adjust the signal level of outputs from an adaptive equalizer to a target value is provided in a stage later than the adaptive equalizer and earlier than a frequency offset estimation/compensation unit in an optical digital coherent receiver. The ALC processing unit generates a histogram that counts the number of samples for discrete monitored values corresponding to amplitude values of outputs from the adaptive equalizer, and determines a level adjustment coefficient that is to be multiplied by an output from the adaptive equalizer so as to multiply the determined coefficient by the output from the adaptive equalizer so that the monitored value of the peak value of the histogram is the target value.

Abstract: In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented.

Abstract: A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

Abstract: In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented.

Abstract: In a BER monitoring circuit, error cycles of input data are detected by a parity check portion and an error cycle detecting portion, a maximum (average/median) value is detected from among the error cycles by an error cycle memory and an error cycle maximum (average/median) value retrieving portion. The value is converted into a corresponding estimated error rate by a Te-BER conversion table and an alarm is generated by an SF/SD detecting -portion when the estimated error rate exceeds an alarm detecting threshold. Thereafter, the alarm is released when the estimated error rate assumes equal to or less than an alarm releasing threshold. Also, an error-free detecting portion is activated when an alarm is generated and releases the alarm when a time period for which the error cycles stay flat exceeds a cycle corresponding to the alarm releasing threshold.

Abstract: An ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree even during multicast processing. The ATM cell bridge apparatus includes a buffer unit for storing cell data of input cells, a buffer control unit for controlling writing and reading out of the cell data into and from the buffer unit, a cell production control unit for managing multicast information of the cell data read out from the buffer unit by the buffer control unit and producing a cell to be outputted from header information of the cell data, and a cell outputting unit for outputting the cell produced by the cell production control unit and issuing a cell data readout request to the buffer control unit.

Abstract: A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

Abstract: The invention provides an ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree of it even during multicast processing and the burden to a transmission source is moderated by intra-port multicast on an ATM transmission apparatus and besides the transmission efficiency of cells having high priority degrees is raised.

Abstract: A digital signal multiplexing apparatus has n (n is an arbitrary integer) multiplexing circuits (11-1n) for converting input signals from a plurality of lines into m (m is an arbitrary integer) parallel signals which are added with added bits and have a first transmission speed. A parallel-serial conversion circuit (40) converts the m parallel signals from the n multiplexing circuits into a serial multiplexed signal by a parallel-serial conversion. A bus (30) connects the n multiplexing circuits and the parallel-serial conversion circuit. The n multiplexing circuits respectively have a circuit for successively transmitting the m parallel signals to the bus using a pluse signal having a second transmission speed which is n times the first transmission speed. A digital signal demultiplexing circuit has a serial-parallel conversion circuit (75) for converting a serial input signal into m (m is an arbitrary integer) parallel signals having a predetermined transmission speed.

Abstract: A complex multiplexer/demultiplexer apparatus which converts input low order group data signals to middle order group data signals and multiplexes them to high order group data signals and converts high order group data signals to middle order group data signals and demultiplexes them to low order group data signals, wherein a plurality of low order group channels are processed by multiplexing and demultiplexing at a second clock bit synchronized with a first clock on the high order group side, the second clock including empty bits, and the bit rate being set lower than the first clock, and signal speeds between each of first multiplexers and a second multiplexer and between a first demultiplexer and each of second demultiplexers are converted by insertion and deletion of the empty bits which may have inserted therein additional information.