Patents by Inventor Yuji Ohmaki

Yuji Ohmaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8242539
    Abstract: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 14, 2012
    Assignee: Nichia Corporation
    Inventor: Yuji Ohmaki
  • Patent number: 7560752
    Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: July 14, 2009
    Assignee: Nichia Corporation
    Inventors: Shiro Akamatsu, Yuji Ohmaki
  • Publication number: 20080173898
    Abstract: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between.
    Type: Application
    Filed: March 14, 2006
    Publication date: July 24, 2008
    Applicant: NICHIA CORPORATION
    Inventor: Yuji Ohmaki
  • Publication number: 20080135854
    Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.
    Type: Application
    Filed: January 7, 2008
    Publication date: June 12, 2008
    Inventors: Shiro Akamatsu, Yuji Ohmaki
  • Patent number: 7339206
    Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: March 4, 2008
    Assignee: Nichia Corporation
    Inventors: Shiro Akamatsu, Yuji Ohmaki
  • Publication number: 20060231861
    Abstract: An FET includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.
    Type: Application
    Filed: March 24, 2006
    Publication date: October 19, 2006
    Applicant: NICHIA CORPORATION
    Inventors: Shiro Akamatsu, Yuji Ohmaki