Abstract: A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.

Abstract: A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.

Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse sets a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

Abstract: An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.

Abstract: A system for computer pipeline operation in which a plurality of instructions are executed in parallel by commencing, before the termination of execution of the preceding instruction, the execution of the present instruction, including a conflict detection unit, a data establishment indication unit, and a source data by-pass unit. The source data by-pass unit by-passes a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.

Abstract: A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse makes a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

Abstract: A system for controlling the transfer of commands between processors of a multiprocessor system, including a single control unit connected to all the processors by separate information transfer lines. The control unit selects the processor generating a command transfer request signal in a predetermined priority order and receives the processor address from the selected processor. The receiving processor and predetermined transfer information are determined in accordance with the selected processor, the processor address, and the processor status information determined by the processor address. The predetermined transfer information is transferred to the receiving processor via an information transfer path established between the selected processor and the receiving processor.

Abstract: According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed.

Abstract: According to the present invention, an instruction address register unit I for reading instructions and an instruction address register unit II for indicating the address of the instruction being executed in the pipeline are provided independently. The address of a branching instruction is held in the instruction address register unit II until said instruction passes through the pipeline, the content of instruction address register unit I is updated when branching of the branching instruction is determined, and thereby delay in reading an instruction after 8 bytes at the branching address can be reduced.

Abstract: A buffer storage control system is provided having a central processing unit having a buffer storage for storing a part of the content of a main storage, wherein, when a block transfer from the main storage to the buffer storage is carried out, data to be processed is transferred directly to an arithmetic unit or an instruction processing unit via a by-pass operation. The transferred data is then written into the buffer storage and only the portion written in a block can be read, even if not all of the data of one block is written into the buffer storage. During the period from the end of the by-pass operation to the end of the write operation into the buffer storage, with respect to data related to the by-pass operation and data transferred from the main storage, subsequent to the data related to the by-pass operation, the access to the buffer storage based upon a subsequent request for access is inhibited.

Abstract: A computer system includes a processing unit; main storage; cache buffer storage provided between the processing unit and the main storage; and a store buffer device between the processing unit and main storage, receiving data identical to that stored in the cache buffer storage and control information in response to requests from the processing unit and transferring the data and control information to main storage. The transmission from the processing unit to the store buffer device and from the store buffer device to main storage are in a machine cycle. The store buffer device includes a controller, data register sets, each set including registers for receiving data to be stored in main storage, a byte mark register set of byte mark registers for information indicating storable data in the data registers, and an address register set of address registers for a starting store address in main storage for the data in the data registers.

Abstract: An error recovery system in a data processor of the pipeline type, including control storage for storing instruction data, having an error correction and detection code adapted to the detection and correction of errors, for controlling the data processor. A parity check circuit checks instructions read from the control storage and stops at least a part of pipeline processing immediately upon the detection of an error. An error correction circuit corrects the error in the read instruction data and rewrites the instruction data into the control storage while the part of the pipeline processing is stopped.

Abstract: A vector data processing system includes at least an A-access pipeline (27) and a B-access pipeline (28) between a main storage unit (4) and vector registers (21). Associated with the A-access pipeline (27) are a write port (WA) and a read port (RA) selectively connected to the vector registers (21). Associated with the B-access pipeline (28) are a write port (WB) and a read port (RB) selectively connected to the vector registers (21). An additional read port (IA) is linked between the read port (RB) of the B-access pipeline (28) and the address input side of the A-access pipeline (27). When an indirect address load/store instruction is carried out for the A-access pipeline (27), an indirect address is generated from the vector registers (21) via the read port (RB) of the B-access pipeline (28) and the additional read port (IA).