Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments use masking factors that re-blind secret data without exposing the unmasked secret data between iterations of the ladder computations. Some disclosed embodiments use Montgomery multiplication techniques to facilitate secret data masking by efficiently avoiding modular division operations. Disclosed embodiments significantly reduce the vulnerability of ladder computations to adversarial side-channel attacks.

Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engines.

Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments balance execution of various iterations in a way that is balanced for different secret values, significantly reducing vulnerability of ladder computations to adversarial side-channel attacks.

Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as Montgomery multiplication with reduced interdependencies, using optimized processing resources.

Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate secure ladder computational operations whose iterative execution depends on secret values associated with input data. Disclosed embodiments use masking factors that re-blind secret data without exposing the unmasked secret data between iterations of the ladder computations. Some disclosed embodiments use Montgomery multiplication techniques to facilitate secret data masking by efficiently avoiding modular division operations. Disclosed embodiments significantly reduce the vulnerability of ladder computations to adversarial side-channel attacks.

Abstract: Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engines.

Abstract: An anti process variation self-adjustable on-chip oscillator has been disclosed according to the present invention. The on-chip oscillator includes the following components integrated on a same chip: a reference oscillation unit for producing reference pulse; an oscillation unit to be adjusted for producing output pulse; and a self-adjustable logic control unit for receiving the reference pulse and output pulse, and for transmitting a corresponding adjustment signal to the oscillation unit to be adjusted based on the received reference pulse and output pulse to control the oscillation unit to be adjusted to perform the frequency adjustment to the output pulse. The reference pulse required for adjusting the frequency can be generated by the reference oscillation unit integrated on-chip, so that self-adjustment can be achieved on-chip, decrease the cost of the chip compared with off-chip adjustment.

Abstract: An anti process variation self-adjustable on-chip oscillator has been disclosed according to the present invention. The on-chip oscillator includes the following components integrated on a same chip: a reference oscillation unit for producing reference pulse; an oscillation unit to be adjusted for producing output pulse; and a self-adjustable logic control unit for receiving the reference pulse and output pulse, and for transmitting a corresponding adjustment signal to the oscillation unit to be adjusted based on the received reference pulse and output pulse to control the oscillation unit to be adjusted to perform the frequency adjustment to the output pulse. The reference pulse required for adjusting the frequency can be generated by the reference oscillation unit integrated on-chip, so that self-adjustment can be achieved on-chip, decrease the cost of the chip compared with off-chip adjustment.