Abstract: A phase classification model of a cloud application deployment device calculates a feature vector for each time period from resource usage data for each time period when an application is executed, clusters the feature vectors for each time period, and validates a result of the clustering to determine which phase the feature vector belongs to. Validation between a feature vector of a new application and a feature vector belonging to a cluster of a known phase is performed, and it is determined whether each time period belongs to the known phase or an unknown phase on the basis of a degree of the validation. The resource usage of a computer node for each phase is inferred, and application deployment is performed on the basis of an inference result.

Abstract: A phase classification model of a cloud application deployment device calculates a feature vector for each time period from resource usage data for each time period when an application is executed, clusters the feature vectors for each time period, and validates a result of the clustering to determine which phase the feature vector belongs to. Validation between a feature vector of a new application and a feature vector belonging to a cluster of a known phase is performed, and it is determined whether each time period belongs to the known phase or an unknown phase on the basis of a degree of the validation. The resource usage of a computer node for each phase is inferred, and application deployment is performed on the basis of an inference result.

Abstract: The prefetch control is optimized according to a data pattern. The model selection unit selects inference units from outside of the device driver and replace each of the inference units according to the type of data analysis. The inference units, each of which is a neural network, predict an address region of the SSD based on I/O trace data collected by the device driver and instruct the device driver to prefetch from the outside based on the prediction result. The prefetch execution unit performs prefetch for the storage cache allocated to the SCM based on the prediction by a neural network associated with the query and the database.

Abstract: An area for prefetching is determined while accommodating an increase in a block address space. A prediction model predicts prefetch addresses for each of bit ranges into which block addresses are split by using a plurality of neural networks assuming charge of the different bit ranges having performed machine learning on I/O trace data, a prediction accuracy determination section determines a size of an area for prefetching on the basis of addresses in the bit range for which prediction accuracy in prefetch is lower than a predetermined value, a predicted value determination section determines addresses of the area for prefetching on the basis of addresses in the bit range for which the prediction accuracy in the prefetch is equal to or higher than the predetermined value, and a prefetch issuance section caches data in the area for prefetching in a storage class memory from a NAND flash memory.

Abstract: The prefetch control is optimized according to a data pattern. The model selection unit selects inference units from outside of the device driver and replace each of the inference units according to the type of data analysis. The inference units, each of which is a neural network, predict an address region of the SSD based on I/O trace data collected by the device driver and instruct the device driver to prefetch from the outside based on the prediction result. The prefetch execution unit performs prefetch for the storage cache allocated to the SCM based on the prediction by a neural network associated with the query and the database.

Abstract: An area for prefetching is determined while accommodating an increase in a block address space. A prediction model predicts prefetch addresses for each of bit ranges into which block addresses are split by using a plurality of neural networks assuming charge of the different bit ranges having performed machine learning on I/O trace data, a prediction accuracy determination section determines a size of an area for prefetching on the basis of addresses in the bit range for which prediction accuracy in prefetch is lower than a predetermined value, a predicted value determination section determines addresses of the area for prefetching on the basis of addresses in the bit range for which the prediction accuracy in the prefetch is equal to or higher than the predetermined value, and a prefetch issuance section caches data in the area for prefetching in a storage class memory from a NAND flash memory.

Abstract: A computer system, comprising a plurality of computers, each of the plurality of computers including at least one processor chip each including a plurality of processor cores, the at least one processor chip constructing a plurality of regions each constructed by at least one processor core, each of the plurality of processor cores carries out calculation processing for executing a predetermined program and inter-core communication processing, which is communication between the plurality of processor cores, the computer system comprising: a regulation module which controls a voltage and a frequency that are supplied to each of the plurality of regions; and a determination module which determines a power mode of each of the plurality of regions, to output an instruction to the regulation module.

Abstract: An information processing apparatus includes a processor, a plurality of storage devices, and an FPGA. The plurality of storage devices stores a plurality of items of segment data. Each item of segment data includes configuration information on a configuration of the segment data. A search command in which search target segment data and a search formula for the database are described is received from a host computer. The FPGA reads the configuration information relating to the search target segment data, analyzes the search formula to specify column data to be used for search, specifies, based on the read configuration information, a storage location of the specified column data in the search target segment data, reads column data to be used by the specified search target from the storage device in which the search target segment data is stored and executes search, and returns the search result to the host computer.

Abstract: A computer system, comprising a plurality of computers, each of the plurality of computers including at least one processor chip each including a plurality of processor cores, the at least one processor chip constructing a plurality of regions each constructed by at least one processor core, each of the plurality of processor cores carries out calculation processing for executing a predetermined program and inter-core communication processing, which is communication between the plurality of processor cores, the computer system comprising: a regulation module which controls a voltage and a frequency that are supplied to each of the plurality of regions; and a determination module which determines a power mode of each of the plurality of regions, to output an instruction to the regulation module.

Abstract: An information processing apparatus includes a processor, a plurality of storage devices, and an FPGA. The plurality of storage devices stores a plurality of items of segment data. Each item of segment data includes configuration information on a configuration of the segment data. A search command in which search target segment data and a search formula for the database are described is received from a host computer. The FPGA reads the configuration information relating to the search target segment data, analyzes the search formula to specify column data to be used for search, specifies, based on the read configuration information, a storage location of the specified column data in the search target segment data, reads column data to be used by the specified search target from the storage device in which the search target segment data is stored and executes search, and returns the search result to the host computer.

Abstract: The present invention provides a patch preparation that has an extremely low moisture permeability, has a sufficient ODT effect, is excellent in drug releasability, and has a preferred handleability. The patch preparation of the present invention includes a support; and a pressure-sensitive adhesive layer containing an adherent polymer and a drug on one surface of the support, wherein: the support has a polyester base layer, an inorganic oxide layer, and a polyester nonwoven fabric layer in the stated order; the polyester base layer has a thickness of 1.0 ?m to 16 ?m; and the pressure-sensitive adhesive layer is laminated on the polyester base layer.

Abstract: Provided is a methylphenidate patch preparation superior in the stability of a drug (methylphenidate and/or a salt thereof) in the patch preparation, skin permeability of a drug during use of the patch preparation, and methylphenidate availability. A patch preparation having a support and an adhesive layer formed on at least one surface of the support, wherein the adhesive layer contains methylphenidate and/or a salt thereof, polyisobutylene and a liquid plasticizer. The liquid plasticizer preferably has an HLB value of 1.0-3.3.

Abstract: The present invention provides a patch preparation that has an extremely low moisture permeability, has a sufficient ODT effect, is excellent in drug releasability and in anchoring property of its drug-containing pressure-sensitive adhesive layer, and has a preferred patch feeling. The patch preparation of the present invention includes a support; and a pressure-sensitive adhesive layer containing an adherent polymer and a drug on one surface of the support, wherein: the support has a polyester base layer, an inorganic oxide layer, and a polyester nonwoven fabric layer in the stated order; the polyester base layer has a thickness of 1.0 ?m to 16 ?m; and the pressure-sensitive adhesive layer is laminated on the polyester nonwoven fabric layer.

Abstract: The present invention provides a patch preparation that has an extremely low moisture permeability, has a sufficient ODT effect, is excellent in drug releasability, and has a preferred handleability. The patch preparation of the present invention includes a support; and a pressure-sensitive adhesive layer containing an adherent polymer and a drug on one surface of the support, wherein: the support has a polyester base layer, an inorganic oxide layer, and a polyester nonwoven fabric layer in the stated order; the polyester base layer has a thickness of 1.0 ?m to 16 ?m; and the pressure-sensitive adhesive layer is laminated on the polyester base layer.

Abstract: The present invention provides a Fentanyl-containing percutaneously absorbable adhesive preparation, which is obtained from economic starting materials, has a constitution simpler than that of conventional ones, has sufficient skin permeability, and which permits control of skin permeability by changing the mixing ratio of two kinds of polyisobutylene having different molecular weights, a tackifier and an organic liquid. Specifically, the present invention provides a percutaneously absorbable adhesive preparation comprising a support and an adhesive layer laminated on one surface thereof, wherein the adhesive layer comprises Fentanyl, two kinds of polyisobutylene having different molecular weights, a tackifier and an organic liquid compatible with the aforementioned two kinds of polyisobutylene and the aforementioned tackifier.

Abstract: The present invention provides an adhesive material to be adhered to the skin etc., which maintains, for a certain time period after adhesion thereof to the skin surface, suitable adhesiveness that does not allow easy peeling or cause irritation to the skin, and which permits, when it is to be peeled off from the skin surface after the lapse of a desired certain time period, easy peeling without causing pain or physical irritation, and an adhesive preparation containing the adhesive material and a percutaneously absorbable drug in the adhesive layer. Specifically, the present invention provides an adhesive material containing a support and an adhesive layer laminated on one surface of the support, wherein the adhesive layer has an apparent viscosity at 30° C. of 0.2×104 to 10×104 Pa·s and comprises two kinds of synthetic rubbers having different flowability.

Abstract: The present invention provides a patch preparation that has an extremely low moisture permeability, has a sufficient ODT effect, is excellent in drug releasability and in anchoring property of its drug-containing pressure-sensitive adhesive layer, and has a preferred patch feeling. The patch preparation of the present invention includes a support; and a pressure-sensitive adhesive layer containing an adherent polymer and a drug on one surface of the support, wherein: the support has a polyester base layer, an inorganic oxide layer, and a polyester nonwoven fabric layer in the stated order; the polyester base layer has a thickness of 1.0 ?m to 16 ?m; and the pressure-sensitive adhesive layer is laminated on the polyester nonwoven fabric layer.

Abstract: Provided is a methylphenidate patch preparation superior in the stability of a drug (methylphenidate and/or a salt thereof) in the patch preparation, skin permeability of a drug during use of the patch preparation, and methylphenidate availability. A patch preparation having a support and an adhesive layer formed on at least one surface of the support, wherein the adhesive layer contains methylphenidate and/or a salt thereof, polyisobutylene and a liquid plasticizer. The liquid plasticizer preferably has an HLB value of 1.0-3.3.

Abstract: When a plurality of OSs are mounted, it is desirable to efficiently use memory resources without affecting other OSs. Also, even if the OSs are different from each other, they are mounted on one system, and therefore, inter-OS communication is required. In this case, data communication without affecting other OSs is required. Accordingly, an information processor includes: a firmware for assigning a first central processing unit, a first operating system, and a first region being a partial region of a memory as a first domain, assigning a second central processing unit, a second operating system, and a second region being a partial region of the memory as a second domain, and controlling to disable an access of one domain to a region assigned for the other domain; and a middleware for controlling a communication when the data communication is required between the first domain and the second domain.

Abstract: The present invention provides a transdermal drug administration device capable of freely controlling release of the drug. The transdermal drug administration device of the present invention contains a backing layer and a matrix layer provided on at least one surface of the backing layer, wherein the matrix layer contains a region located on a proximal side from the backing layer and a region located on a distal side from the backing layer, and the water-absorbing polymers therein have different weight concentrations, which enables high control of a drug released from the device.