Patents by Inventor Yuji Segawa

Yuji Segawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6551472
    Abstract: An electroforming apparatus comprising a container unit for storing the plating solution, a cathode part placed in the container unit and for holding an object to-be-plated and an anode part placed in the container unit face-to-face with the cathode part, wherein a current-conductive opening of the anode part is formed to have an area larger than that of a current-conductive opening of the cathode part.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: April 22, 2003
    Assignee: Sony Corporation
    Inventors: Eiji Saito, Masatoshi Suzuki, Minoru Tazoe, Makoto Ito, Yuji Segawa
  • Patent number: 6534117
    Abstract: When a barrier layer formed on a surface of a contact hole is subjected to electroless plating of copper, a salt of a metal such as gold, nickel, palladium, cobalt or platinum is added as a plating accelerator in an amount of 1 mol % or less based on a copper salt in a composition of an electroless plating solution, whereby the metal having the higher catalytic activity than copper is precipitated before precipitation of copper, and copper can then be precipitated as a good-quality plated film.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: March 18, 2003
    Assignee: Sony Corporation
    Inventors: Akira Yoshio, Yuji Segawa, Naoki Komai
  • Patent number: 6509791
    Abstract: The switched capacitor filter circuit comprises an amplifier whose feedback capacitance Cf is variable. This feedback capacitance is changed based on the control signals received from the outside. Two switches control charging/discharging of a first capacitor. Another Two switches control charging/discharging of a second capacitor. Frequency f1 of a signal for switching the four switches is changed so that a beat frequency varies within a range having no influence with respect to a cutoff frequency while always keeping a value of the f1/Cf constant.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 21, 2003
    Assignee: Fujitsu Limited
    Inventors: Yuji Segawa, Asao Kokubo
  • Publication number: 20020167353
    Abstract: The switched capacitor filter circuit comprises an amplifier whose feedback capacitance Cf is variable. This feedback capacitance is changed based on the control signals received from the outside. Two switches control charging/discharging of a first capacitor. Another Two switches control charging/discharging of a second capacitor. Frequency f1 of a signal for switching the four switches is changed so that a beat frequency varies within a range having no influence with respect to a cutoff frequency while always keeping a value of the f1/Cf constant.
    Type: Application
    Filed: January 18, 2002
    Publication date: November 14, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Segawa, Asao Kokubo
  • Patent number: 6479384
    Abstract: A process for fabricating a semiconductor device, which comprises forming, on a metal wiring formed from copper or a copper alloy, a barrier film which functions as a diffusion-preventing film for the metal wiring by an electroless plating method, wherein a catalytic metal film which serves as a catalyst in the electroless plating method is selectively formed on the metal wiring by a displacement plating method using a displacement plating solution at a temperature in the range of 30° C. or more and lower than a boiling point thereof, and the barrier film is selectively formed on the catalytic metal film by the electroless plating method. It is an object of the present invention, to selectively and uniformly carry out the catalyst activation to the surface of the metal wiring made of copper or a copper alloy by using palladium so as to improve plating property of the electroless plating method using a hypophosphite as a reducing agent and the reliability of the wiring.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: November 12, 2002
    Assignee: Sony Corporation
    Inventors: Naoki Komai, Yuji Segawa, Takeshi Nogami
  • Patent number: 6456170
    Abstract: The inverter functioning as a comparator, dummy inverter having the same electric characteristics as the inverter, and control circuit are provided. Vth detecting input voltage output from the control circuit is input into the dummy inverter, Vth detecting output voltage output from the dummy inverter is input into the control circuit, and the threshold voltage of the dummy inverter is detected. The threshold voltage of the inverter is controlled by controlling the back gate voltages of the MOS transistors of the dummy inverter and the inverter in such a manner that the threshold voltage of the dummy inverter coincide with an external reference voltage.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: September 24, 2002
    Assignee: Fujitsu Limited
    Inventors: Yuji Segawa, Masaru Otsuka, Osamu Kikuchi, Akira Haga, Yoshinori Yoshikawa
  • Publication number: 20020070126
    Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.
    Type: Application
    Filed: September 19, 2001
    Publication date: June 13, 2002
    Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
  • Publication number: 20020072309
    Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishin
    Type: Application
    Filed: September 26, 2001
    Publication date: June 13, 2002
    Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
  • Publication number: 20020036143
    Abstract: A method of electroless plating for processing a plating surface to form a barrier layer being capable of uniformly forming a barrier layer and reducing the consumption of a processing solution, comprising a step of feeding a processing solution used in at least one of the pre-processing steps of the electroless plating and the electroless plating step to the plating surface for puddling treatment, or, using a processing solution at least containing, with respect to one mole of a first metallic material supplying a main ingredient of the barrier layer, three or more moles of a completing agent and three or more moles of reducing agent and having a pH value adjusted to 9 or more and stored in an atmosphere of an inert gas or ammonia gas, and a corresponding electroless plating apparatus.
    Type: Application
    Filed: April 9, 2001
    Publication date: March 28, 2002
    Inventors: Yuji Segawa, Akira Yoshio, Masatoshi Suzuki, Katsumi Watanabe, Shuzo Sato
  • Publication number: 20020023833
    Abstract: An electroforming apparatus comprises a container unit for storing a plating solution, a cathode part placed in the container unit and for holding an object to-be-plated and an anode part placed in the container unit face-to-face with the cathode part, wherein a current-conductive opening of the anode part is formed to have an area larger than that of a current-conductive opening of the cathode part.
    Type: Application
    Filed: June 13, 2001
    Publication date: February 28, 2002
    Inventors: Eiji Saito, Masatoshi Suzuki, Minoru Tazoe, Makoto Ito, Yuji Segawa
  • Patent number: 6342818
    Abstract: A cut-off state of a carrier signal or a carrier signal outside an effective range of a frequency is detected by a carrier detector, and a signal switching circuit inputs a clock 2 from an external device into a phase comparator in place of the carrier signal, with which a locked state is maintained in a PLL comprising the phase comparator, a charge pump, a loop filter, a voltage control oscillator, and a 1/N divider, so that a high-speed locking operation is realized to another appropriate carrier signal.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: January 29, 2002
    Assignee: Fujitsu Limited
    Inventors: Yuji Segawa, Kunihiko Gotoh
  • Publication number: 20020003453
    Abstract: A cut-off state of a carrier signal or a carrier signal outside an effective range of a frequency is detected by a carrier detector, and a signal switching circuit inputs a clock 2 from an external device into a phase comparator in place of the carrier signal, with which a locked state is maintained in a PLL comprising the phase comparator, a charge pump, a loop filter, a voltage control oscillator, and a 1/N divider, so that a high-speed locking operation is realized to another appropriate carrier signal.
    Type: Application
    Filed: May 17, 1999
    Publication date: January 10, 2002
    Inventors: YUJI SEGAWA, KUNIHIKO GOTOH
  • Publication number: 20010036746
    Abstract: A method of production and a method of polishing a semiconductor device and a polishing apparatus, capable of easily flattening an initial unevenness of a metal film, excellent in efficiency of removal of an excess metal film, and capable of suppressing damage to an interlayer insulation film below the metal film when flattening the metal film by polishing, the polishing method including the steps of interposing an electrolytic solution including a chelating agent between a cathode member and the copper film, applying a voltage between the cathode member used as a cathode and the copper film used as an anode to oxidize the surface of the copper film and forming a chelate film of the oxidized copper, selectively removing a projecting portion of the chelate film corresponding to the shape of the copper film to expose the projecting portion of the copper film at its surface, and repeating the above chelate film forming step and the above chelate film removing step until the projecting portion of the copper film
    Type: Application
    Filed: March 8, 2001
    Publication date: November 1, 2001
    Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Hiizu Ootorii, Zenya Yasuda, Masao Ishihara, Takeshi Nogami, Naoki Komai
  • Publication number: 20010019892
    Abstract: A process for fabricating a semiconductor device, which comprises forming, on a metal wiring formed from copper or a copper alloy, a barrier film which functions as a diffusion-preventing film for the metal wiring by an electroless plating method, wherein a catalytic metal film which serves as a catalyst in the electroless plating method is selectively formed on the metal wiring by a displacement plating method using a displacement plating solution at a temperature in the range of 30° C. or more and lower than a boiling point thereof, and the barrier film is selectively formed on the catalytic metal film by the electroless plating method. It is an object of the present invention, to selectively and uniformly carry out the catalyst activation to the surface of the metal wiring made of copper or a copper alloy by using palladium so as to improve plating property of the electroless plating method using a hypophosphite as a reducing agent and the reliability of the wiring.
    Type: Application
    Filed: February 15, 2001
    Publication date: September 6, 2001
    Inventors: Naoki Komai, Yuji Segawa, Takeshi Nogami
  • Patent number: 6211746
    Abstract: Disclosed are an integration circuit capable of substantially raising the ratio of a current to a capacitance, I/C, and voltage-controlled oscillator and frequency-voltage converter which employ the integration circuit. The integration circuit comprises an integrating capacitor, a current source, a switch, a detection circuit, and a control circuit. The current source supplies a current to the integrating capacitor. The switch is installed on a path along which a current is supplied from the current source to the integrating capacitor. The detection circuit detects a voltage developed at the integrating capacitor. The control circuit controls the switch so that a current will be supplied from the current source to the integrating capacitor during an integration period. The integration period falls into a current supply period and a stop period.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: April 3, 2001
    Assignee: Fujitsu Limited
    Inventors: Yuji Segawa, Kunihiko Gotoh
  • Patent number: 6100766
    Abstract: A correction circuit for controlling a correction required circuit includes an oscillator circuit, and a logic circuit which counts an oscillation frequency of the oscillator circuit and thus produces a control signal which causes the oscillator circuit to oscillate at a constant frequency. The control signal changes element values of elements of the oscillator circuit and the correction required circuit so that characteristics of the oscillator circuit and the correction required circuit can be controlled.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: August 8, 2000
    Assignee: Fujitsu Limited
    Inventors: Yuji Segawa, Kunihiko Gotoh
  • Patent number: 6064243
    Abstract: The present invention is a current switch, which supplies a constant current to a load circuit, and comprises: a transistor, the gate of which is supplied with a predetermined constant voltage, and the drain of which is connected to the above-mentioned load circuit; and a constant voltage supply circuit, which, in response to a control signal, supplies to the source of the above-mentioned transistor a first constant voltage, or a second constant voltage that differs from the first constant voltage, wherein when the above-mentioned first constant voltage is supplied to the above-mentioned transistor source by the above-mentioned constant voltage supply circuit, the transistor is turned ON and supplies the above-mentioned constant current to the above-mentioned load circuit, and when the above-mentioned secondary constant voltage is supplied to the above-mentioned transistor source, the transistor is turned OFF and interrupts the above-mentioned constant current.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: May 16, 2000
    Assignee: Fujitsu Limited
    Inventors: Atsushi Matsuda, Yuji Segawa, Kunihiko Gotoh
  • Patent number: 5955925
    Abstract: An AGC circuit according to the present invention comprises: a gain controller, having a variable gain, for amplifying an input signal at a predetermined gain and generating an output signal, and for varying the gain; a comparison circuit for comparing an amplitude of the input signal or of the output signal with a predetermined reference level, and for generating a control signal that goes to a first level when the amplitude is smaller than the reference level, and that goes to a second level when the amplitude is greater than the reference level; and a duty ratio detector for supplying the control signal generated by the comparison circuit, and for generating control code in accordance with a duty ratio of the control signal, wherein the gain of the gain controller is varied by using the control code, and so adjusted that the duty ratio of the control signal is maintained to be a predetermined value.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: September 21, 1999
    Assignee: Fujitsu Limited
    Inventors: Yuji Segawa, Kunihiko Gotoh
  • Patent number: 5870000
    Abstract: An oscillation circuit for producing an output whose frequency accords with an input voltage value, comprises a first constant current source whose current has a value according to the input voltage value; a charge capacitor to be charged by the first constant current source; a comparator having one input terminal connected to a charge terminal of the charge capacitor to be charged and an other input terminal supplied with a first reference voltage, for comparing inputs to both input terminals with each other and outputting an output signal having a high level or a low level; and first switch means for pulling down a potential of the charge terminal of the charge capacitor to a second reference voltage lower than the first reference voltage under control by an output of the comparator.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: February 9, 1999
    Assignee: Fujitsu Limited
    Inventors: Atsushi Matsuda, Yuji Segawa
  • Patent number: 5793257
    Abstract: A voltage-controlled oscillator has first and second switched capacitor filters, an operational amplifier, and a comparator. The first switched capacitor filter is controlled by a control clock signal to supply a positive current depending on an input voltage, and the second switched capacitor filter is controlled by the control clock signal to supply a negative current depending on the input voltage. The operational amplifier has an input terminal alternately connectable to the first and second switched capacitor filters by a first switch which can be rendered conductive in synchronism with an output clock signal, and another input terminal for being supplied with a constant voltage.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: August 11, 1998
    Assignee: Fujitsu Limited
    Inventors: Noboru Inanami, Yuji Segawa, Kunihiko Gotoh