Patents by Inventor Yuji Shintomi
Yuji Shintomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11609875Abstract: A data communication device includes: a fixed value memory that stores a fixed value; a received data memory that stores received data inputted through a bus; an output data memory that stores output data; a comparison determination unit that outputs a comparison determination result signal indicating a determination result of comparing the fixed value and a value of the received data; a data output unit that has a first state of outputting the output data to the bus and a second state of not outputting the output data to the bus; a command analyzing unit that outputs a data output control signal based on a command; and an output controller that outputs a control signal for controlling the data output unit to enter the first state or the second state based on the comparison determination result signal and the data output control signal.Type: GrantFiled: March 25, 2021Date of Patent: March 21, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuhiro Nakamuta, Yuji Shintomi, Satoshi Matsumura, Toshiki Matsumura, Satoru Matsuyama
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Publication number: 20210303502Abstract: A data communication device includes: a fixed value memory that stores a fixed value; a received data memory that stores received data inputted through a bus; an output data memory that stores output data; a comparison determination unit that outputs a comparison determination result signal indicating a determination result of comparing the fixed value and a value of the received data; a data output unit that has a first state of outputting the output data to the bus and a second state of not outputting the output data to the bus; a command analyzing unit that outputs a data output control signal based on a command; and an output controller that outputs a control signal for controlling the data output unit to enter the first state or the second state based on the comparison determination result signal and the data output control signal.Type: ApplicationFiled: March 25, 2021Publication date: September 30, 2021Inventors: Kazuhiro NAKAMUTA, Yuji SHINTOMI, Satoshi MATSUMURA, Toshiki MATSUMURA, Satoru MATSUYAMA
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Patent number: 11070239Abstract: An interface circuit and a communication apparatus that can reduce the circuit scale and power consumption are provided. An interface circuit includes a plurality of communication devices, an analog-to-digital (AD) conversion circuit that converts an analog signal to digital data, and a control circuit that reads the digital data in response to read-request signals received from the plurality of communication devices.Type: GrantFiled: December 12, 2019Date of Patent: July 20, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Toshiki Matsumura, Yuji Shintomi, Satoshi Matsumura, Kazuhiro Nakamuta
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Patent number: 10985710Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.Type: GrantFiled: May 6, 2020Date of Patent: April 20, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
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Publication number: 20200266773Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.Type: ApplicationFiled: May 6, 2020Publication date: August 20, 2020Inventors: Shota ISHIHARA, Yuji SHINTOMI, Satoshi MATSUMURA
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Publication number: 20200195281Abstract: An interface circuit and a communication apparatus that can reduce the circuit scale and power consumption are provided. An interface circuit includes a plurality of communication devices, an analog-to-digital (AD) conversion circuit that converts an analog signal to digital data, and a control circuit that reads the digital data in response to read-request signals received from the plurality of communication devices.Type: ApplicationFiled: December 12, 2019Publication date: June 18, 2020Inventors: Toshiki MATSUMURA, Yuji SHINTOMI, Satoshi MATSUMURA, Kazuhiro NAKAMUTA
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Patent number: 10680561Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.Type: GrantFiled: January 31, 2019Date of Patent: June 9, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
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Patent number: 10567117Abstract: A transfer device includes: a converter configured to convert an address contained in a command CMD1 transmitted from a master device, to an address indicating an internal slave device, and transfer a command CMD2K to the stated internal slave device; a first parity calculator configured to calculate a first parity bit formed of one bit for the command CMD2K; and a judgment circuit configured to judge whether or not a predetermined abort condition is satisfied. When the predetermined abort condition is satisfied, the converter outputs the first parity bit as a parity bit of the command CMD2K.Type: GrantFiled: June 8, 2018Date of Patent: February 18, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Yuji Shintomi
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Patent number: 10566998Abstract: A first parity calculator calculates one parity bit for serial binary data to be subjected to a conversion process. A second parity calculator calculates one parity bit for serial binary data obtained as a result of the conversion process. When both parity bits do not match, a multiplexer outputs, as a parity bit of the serial binary data obtained as a result of the conversion process, a parity bit obtained by inverting one parity bit included in the serial binary data to be subjected to the conversion process.Type: GrantFiled: April 4, 2018Date of Patent: February 18, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Yuji Shintomi
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Publication number: 20190165742Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
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Patent number: 10236834Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.Type: GrantFiled: August 22, 2017Date of Patent: March 19, 2019Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
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Patent number: 10210130Abstract: Circuits and methods for efficient interconnect layout of multiple circuit elements, including integrated circuits (ICs), within a circuit module, while enabling only a single control/status (C/S) connection per module. In a first embodiment, the C/S interfaces of multiple ICs are configured in parallel within a multi-IC module, and coupled through a single module serial bus to a system C/S serial bus. In a second embodiment, the C/S interface of a primary IC is coupled through a single module serial bus to a system C/S serial bus, while a secondary IC is internally serially coupled to a “pass through” interface of the primary IC. In a third embodiment, a dynamic address translation circuit translates device and register address information provided by a master device into corresponding internal addresses, and re-directs command messages from a system C/S serial bus to internal slave devices.Type: GrantFiled: November 1, 2016Date of Patent: February 19, 2019Assignee: pSemi CorporationInventors: David Alan Podsiadlo, Yuji Shintomi
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Publication number: 20180359055Abstract: A transfer device includes: a converter configured to convert an address contained in a command CMD1 transmitted from a master device, to an address indicating an internal slave device, and transfer a command CMD2K to the stated internal slave device; a first parity calculator configured to calculate a first parity bit formed of one bit for the command CMD2K; and a judgment circuit configured to judge whether or not a predetermined abort condition is satisfied. When the predetermined abort condition is satisfied, the converter outputs the first parity bit as a parity bit of the command CMD2K.Type: ApplicationFiled: June 8, 2018Publication date: December 13, 2018Inventor: Yuji Shintomi
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Publication number: 20180294821Abstract: A first parity calculator calculates one parity bit for serial binary data to be subjected to a conversion process. A second parity calculator calculates one parity bit for serial binary data obtained as a result of the conversion process. When both parity bits do not match, a multiplexer outputs, as a parity bit of the serial binary data obtained as a result of the conversion process, a parity bit obtained by inverting one parity bit included in the serial binary data to be subjected to the conversion process.Type: ApplicationFiled: April 4, 2018Publication date: October 11, 2018Inventor: Yuji SHINTOMI
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Patent number: 10095644Abstract: Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.Type: GrantFiled: September 22, 2017Date of Patent: October 9, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kazuhiro Nakamuta, Yuji Shintomi, Satoshi Matsumura, Masanori Iijima
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Patent number: 9964595Abstract: A register circuit for which an initial value can be changed without using a flip-flop including both a set terminal and a reset terminal is provided. The register circuit includes an initial value wiring line, a write signal terminal, a clock signal terminal, a first flip-flop, an output control circuit, a second flip-flop, and a selector.Type: GrantFiled: August 9, 2017Date of Patent: May 8, 2018Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masanori Iijima, Yuji Shintomi, Satoshi Matsumura
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Publication number: 20180121384Abstract: Circuits and methods for efficient interconnect layout of multiple circuit elements, including integrated circuits (ICs), within a circuit module, while enabling only a single control/status (C/S) connection per module. In a first embodiment, the C/S interfaces of multiple ICs are configured in parallel within a multi-IC module, and coupled through a single module serial bus to a system C/S serial bus. In a second embodiment, the C/S interface of a primary IC is coupled through a single module serial bus to a system C/S serial bus, while a secondary IC is internally serially coupled to a “pass through” interface of the primary IC. In a third embodiment, a dynamic address translation circuit translates device and register address information provided by a master device into corresponding internal addresses, and re-directs command messages from a system C/S serial bus to internal slave devices.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: David Alan Podsiadlo, Yuji Shintomi
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Publication number: 20180089121Abstract: Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device includes: a clock generator circuit that generates a second serial clock signal, the second serial clock signal being synchronized with a first serial clock signal transmitted from a master device; a determination circuit that determines whether a request from the master device is addressed to the data transfer device or not; and a data processing circuit that operates by receiving a transfer of the first serial clock signal from the clock generator circuit on condition of the request from the master device being determined to be addressed to the data transfer device.Type: ApplicationFiled: September 22, 2017Publication date: March 29, 2018Inventors: Kazuhiro Nakamuta, Yuji Shintomi, Satoshi Matsumura, Masanori Iijima
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Publication number: 20180062590Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.Type: ApplicationFiled: August 22, 2017Publication date: March 1, 2018Inventors: Shota Ishihara, Yuji Shintomi, Satoshi Matsumura
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Patent number: 9866195Abstract: A stray capacitance is generated between an antenna element and a ground electrode. A capacitance detection circuit detects the stray capacitance. An antenna matching circuit, is provided along a wireless communication signal path, which is a transmission path between the antenna element and a feeder circuit. A feedback control circuit transmits a control signal to the variable matching circuit on the basis of a detection result of the capacitance detection circuit in accordance with the stray capacitance. The capacitance detection circuit includes a constant current source and a timing circuit to measure the time taken to charge the antenna from the constant current source and for the voltage to reach a predetermined voltage.Type: GrantFiled: July 11, 2017Date of Patent: January 9, 2018Assignee: Murata Manufacturing Co., Ltd.Inventors: Shoji Nagumo, Masashi Nakazato, Motoyasu Nakao, Yuji Shintomi