Abstract: A protocol analyzer of the present disclosure includes a protocol check circuit that relays a control plane and a user plane between a radio unit and a base band unit while performing detection of an error in the control plane and the user plane, and a failure detection packet generation unit configured to generate a failure detection packet based on error factor information generated by the protocol check circuit in response to detection of the error in the control plane and the user plane and based on the ether head of the control plane or the user plane in which the error has been detected and a timestamp, in which the protocol check circuit interprets the control plane and the user plane based on information in a management plane that determines transmission-reception conditions for the control plane and the user plane between the radio unit and the base band unit.

Abstract: A programmable device connected to a storage unit which stores logic circuit configuration information to form a logic circuit and control circuit configuration information to form a control circuit includes a first programmable logic device and a second programmable logic device, and a configuration unit which forms the control circuit in the first programmable logic device, by providing the control circuit configuration information in the storage unit to the first programmable logic device. The control circuit formed in the first programmable logic device forms the logic circuit in the second programmable logic device, by providing the logic circuit configuration information in the storage unit to the second programmable logic device.