Patents by Inventor Yuji Sugaya
Yuji Sugaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923775Abstract: Provided is an in-vehicle power conversion device in which a smoothing capacitor includes a first electrical connection portion, a second electrical connection portion, a mechanical connection portion, and a smoothing capacitor main body. The first electrical connection portion is electrically connected to a first conductor. The second electrical connection portion is electrically connected to a second conductor. The mechanical connection portion functions as an additional electrical connection portion configured to fix the smoothing capacitor main body to the first conductor or the second conductor to be electrically connected to a fixing destination of the smoothing capacitor main body.Type: GrantFiled: December 28, 2018Date of Patent: March 5, 2024Assignee: Mitsubishi Electric CorporationInventors: Yuji Sugaya, Kosuke Inoue, Naoya Yabuuchi
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Publication number: 20210384834Abstract: Provided is an in-vehicle power conversion device in which a smoothing capacitor includes a first electrical connection portion, a second electrical connection portion, a mechanical connection portion, and a smoothing capacitor main body. The first electrical connection portion is electrically connected to a first conductor. The second electrical connection portion is electrically connected to a second conductor. The mechanical connection portion functions as an additional electrical connection portion configured to fix the smoothing capacitor main body to the first conductor or the second conductor so as to be electrically connected to a fixing destination of the smoothing capacitor main body.Type: ApplicationFiled: December 28, 2018Publication date: December 9, 2021Applicant: Mitsubishi Electric CorporationInventors: Yuji SUGAYA, Kosuke INOUE, Naoya YABUUCHI
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Patent number: 10128038Abstract: An isolation transformer wherein in a first coil group of a pair of coil groups provided in an isolation transformer, an inner peripheral side lead wire is drawn out in a positive direction of a z axis and then drawn out to an outer peripheral side of a primary side coil as a first inner peripheral side lead wire, and in a second coil group, the inner peripheral side lead wire is drawn out in a negative direction of the z axis and then drawn out to the outer peripheral side of the primary side coil as a second inner peripheral side lead wire. The first inner peripheral side lead wire and the second inner peripheral side lead wire are then connected to each other, such that respective inner peripheral side end portions are connected to each other in series.Type: GrantFiled: November 17, 2015Date of Patent: November 13, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kodai Katagiri, Takuto Yano, Atsutoshi Takada, Yujiro Kido, Yuji Sugaya
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Publication number: 20180040415Abstract: An isolation transformer wherein in a first coil group of a pair of coil groups provided in an isolation transformer, an inner peripheral side lead wire is drawn out in a positive direction of a z axis and then drawn out to an outer peripheral side of a primary side coil as a first inner peripheral side lead wire, and in a second coil group, the inner peripheral side lead wire is drawn out in a negative direction of the z axis and then drawn out to the outer peripheral side of the primary side coil as a second inner peripheral side lead wire. The first inner peripheral side lead wire and the second inner peripheral side lead wire are then connected to each other, such that respective inner peripheral side end portions are connected to each other in series.Type: ApplicationFiled: November 17, 2015Publication date: February 8, 2018Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kodai KATAGIRI, Takuto YANO, Atsutoshi TAKADA, Yujiro KIDO, Yuji SUGAYA
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Patent number: 6718426Abstract: A cache memory apparatus is provided with a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group, an address managment table for managing both an address and a range with respect to the cache memory into which the information is stored, and a selection circuit for selecting the cache memory in response to an access to the address management table. As a result, information related to a system control is stored into the cache memory apparatus.Type: GrantFiled: February 26, 2001Date of Patent: April 6, 2004Assignee: Hitachi, Ltd.Inventors: Hidemitsu Naya, Hideyuki Okamoto, Koji Kawaki, Yuji Sugaya, Yuichiro Morita, Yoshitaka Takahashi
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Publication number: 20020029365Abstract: An information processing apparatus having a CPU, a memory and a memory controller. The CPU includes a burst access interface for rapidly transferring data, and a single access interface for partial write operations. The memory controller comprises two ECC controllers, one for burst access and the other for single access. Either burst access mode or single access mode can be selected, so that both ECC-based high reliability and a high-speed memory access capability are made available.Type: ApplicationFiled: August 10, 2001Publication date: March 7, 2002Inventors: Yoshimichi Sato, Shoji Yoshida, Shigeya Tanaka, Takashi Hotta, Yuji Sugaya
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Publication number: 20020013877Abstract: A cache memory apparatus is provided with a cache memory for storing thereinto at least one of information about an instruction group related to a system control and information about a data group, an address managment table for managing both an address and a range with respect to the cache memory into which the information is stored, and a selection circuit for selecting the cache memory in response to an access to the address management table. As a result, information related to a system control is stored into the cache memory apparatus.Type: ApplicationFiled: February 26, 2001Publication date: January 31, 2002Inventors: Hidemitsu Naya, Hideyuki Okamoto, Koji Kawaki, Yuji Sugaya, Yuichiro Morita, Yoshitaka Takahashi
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Publication number: 20010023472Abstract: The present invention is to realize a data storage control method and apparatus for an external storage device using flash memories. The method and apparatus can eliminate the data erasure waiting time, eliminating the calculation of the erasure numbers of flash memories, elongating the life-time of the flash memories. Data is stored sequentially from a first flash memory for rewrite data to a third flash memory for rewrite data. When there is no vacant area in the third flash memory for rewrite data, a CPU instructs a first flash memory for garbage collection among the first and second flash memories for garbage collection to perform the garbage collection of the first flash memory for rewrite data. When a host computer issues a write access request, the write process is performed in the first flash memory for garbage collection with the first priority.Type: ApplicationFiled: October 16, 1998Publication date: September 20, 2001Inventors: NORIKO KUBUSHIRO, YUJI SUGAYA
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Patent number: 6205517Abstract: A CPU and a DMA device employ in common an address area from which data cannot be loaded into a cache memory. A read buffer memory and a write buffer memory loading therein data read from and written into that address area are provided. In read access from the CPU or DMA device to the common address area, if data to be accessed exists in any buffer memory, the data in the buffer memory is transferred to the CPU or DMA device. If data to be accessed does not exist in any buffer memory, data at addresses different from the read access address from the CPU or DMA device only in lower bits of fixed length is read from the main memory unit and then loaded into the buffer memory after performing data error checking and correcting of the read data.Type: GrantFiled: April 3, 1997Date of Patent: March 20, 2001Assignee: Hitachi, Ltd.Inventor: Yuji Sugaya
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Patent number: 5551789Abstract: A cosmetic material container comprises: a sleeve holder 1 having an open front end 12 and an open rear end 11; a tail plug 2 for closing the open rear end 11 of the sleeve holder 1; an applying tip unit 3 secured to an open front end side of the sleeve holder 1; and a double cap unit 4 attachably and detachably coupled to the sleeve holder 1 on the outer periphery of its front end 12, the applying tip unit 3 including an adjuster 31 provided on its outer periphery with annular grooves 311, a porous joining core 32 inserted into an axial hole 312 in the adjuster 31 and communicating with a part of the annular grooves 31, and a porous tip 33 connected to a front end of the joining core 32 and inserted in a socket 313 provided in a front end of the adjuster 31, a cosmetic material reservoir 13 being defined between a rear end of the adjuster 31 and the tail end 2 in the sleeve holder 1, and the porous joining core 32 being disposed in the adjuster 31 to project its rear end in the reservoir 13.Type: GrantFiled: October 4, 1994Date of Patent: September 3, 1996Assignee: Kawakami Giken Co LtdInventors: Akira Okawa, Yuji Sugaya