Patents by Inventor Yuji Takayanagi

Yuji Takayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230282561
    Abstract: The provided power semiconductor module is configured to reduce the wiring inductance and save space on the substrate by establishing a multi-parallel connection between multiple power semiconductor chips. It consists of a first and second insulated substrates with a plurality of semiconductor switching elements positioned on one and facing the other. There are also first and second spacer conductors positioned between the plurality of semiconductor switching elements and the second insulated substrate. Inter-spacer-conductor wiring parts are connected with the plurality of second spacer conductors.
    Type: Application
    Filed: April 19, 2021
    Publication date: September 7, 2023
    Applicant: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Toru Masuda, Seiichi Hayakawa, Yuji Takayanagi
  • Patent number: 11539361
    Abstract: To provide a semiconductor device signal transmission circuit for drive-control, a method of controlling a semiconductor device signal transmission circuit for drive-control, a semiconductor device, a power conversion device, and an electric system for a railway vehicle capable of preventing malfunction due to noise while speeding up or reducing loss of a switching operation. The semiconductor device signal transmission circuit for drive-control that is connected between a semiconductor device constituting an arm in a power conversion device and a drive circuit configured to drive the semiconductor device, including: an inductor; and an impedance circuit including a switch and connected in parallel with the inductor.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: December 27, 2022
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Toru Masuda, Seiichi Hayakawa, Yuji Takayanagi, Takae Shimada, Takashi Wada
  • Patent number: 11496041
    Abstract: The invention provides a gate drive device, a gate drive method, a power semiconductor module, and an electric power conversion device capable of reducing a negative gate surge voltage. The gate drive device drives a semiconductor device constituting an arm in an electric power conversion device. Before a turn-off start of a drive arm, in a counter arm, a voltage between one main terminal of the semiconductor device and a gate terminal of the semiconductor device is charged to a voltage value that is larger, in a positive direction, than a negative voltage of a negative gate power supply and smaller than a gate threshold voltage of the semiconductor device.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 8, 2022
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Daisuke Ikarashi, Toru Masuda, Seiichi Hayakawa, Yuji Takayanagi, Masamitsu Inaba
  • Publication number: 20220302075
    Abstract: There is provided a power semiconductor module with multiple semiconductor chips arranged in parallel on an insulated substrate, allowing for high density mounting of semiconductor chips and highly reliable with less difference in operating characteristics from one semiconductor chip to another. The above module includes an insulated substrate; a first conductive pattern laid out on the insulated substrate; multiple power semiconductor chips arranged on the first conductive pattern; a first wiring formed to bridge and directly connecting respective gate electrodes of the power semiconductor chips; and a second wiring formed to bridge and directly connecting respective source electrodes of the power semiconductor chips, wherein the first wiring is placed alongside of the second wiring and may be angled within 30 degrees with respect to the second wiring.
    Type: Application
    Filed: April 6, 2020
    Publication date: September 22, 2022
    Applicant: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Toru Masuda, Seiichi Hayakawa, Yuji Takayanagi
  • Publication number: 20210296979
    Abstract: The invention provides a gate drive device, a gate drive method, a power semiconductor module, and an electric power conversion device capable of reducing a negative gate surge voltage. The gate drive device drives a semiconductor device constituting an arm in an electric power conversion device. Before a turn-off start of a drive arm, in a counter arm, a voltage between one main terminal of the semiconductor device and a gate terminal of the semiconductor device is charged to a voltage value that is larger, in a positive direction, than a negative voltage of a negative gate power supply and smaller than a gate threshold voltage of the semiconductor device.
    Type: Application
    Filed: January 28, 2021
    Publication date: September 23, 2021
    Inventors: Daisuke IKARASHI, Toru MASUDA, Seiichi HAYAKAWA, Yuji TAKAYANAGI, Masamitsu INABA
  • Publication number: 20210288640
    Abstract: To provide a semiconductor device signal transmission circuit for drive-control, a method of controlling a semiconductor device signal transmission circuit for drive-control, a semiconductor device, a power conversion device, and an electric system for a railway vehicle capable of preventing malfunction due to noise while speeding up or reducing loss of a switching operation. The semiconductor device signal transmission circuit for drive-control that is connected between a semiconductor device constituting an arm in a power conversion device and a drive circuit configured to drive the semiconductor device, including: an inductor; and an impedance circuit including a switch and connected in parallel with the inductor.
    Type: Application
    Filed: February 10, 2021
    Publication date: September 16, 2021
    Inventors: Toru MASUDA, Seiichi HAYAKAWA, Yuji TAKAYANAGI, Takae SHIMADA, Takashi WADA
  • Patent number: 5635734
    Abstract: An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: June 3, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Takayanagi, Hideo Kobayashi, Shuroku Sakurada, Hidekatsu Onose
  • Patent number: 5459338
    Abstract: A gate turn-off thyristor having a p-emitter layer in the anode side, an n-base layer, a p-base layer and an n-emitter layer in the cathode side. The n-base layer is composed of a first layer portion adjacent to the p-emitter layer, a second layer portion adjacent to the p-base layer and having a lower impurity concentration than the first layer portion, and is constituted by a structure which alters a travelling path of positive holes injected from the p-emitter layer.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: October 17, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Takayanagi, Susumu Murakami, Yukimasa Satou, Satoshi Matsuyoshi, Yasuhiro Mochizuki, Hidekatsu Onose