Patents by Inventor Yuji Takeuchi
Yuji Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130270622Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: March 15, 2013Publication date: October 17, 2013Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 8421143Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: March 15, 2012Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 8422301Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.Type: GrantFiled: June 27, 2011Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Eietsu Takahashi, Yuji Takeuchi
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Patent number: 8405139Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: April 13, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20130058170Abstract: A nonvolatile semiconductor storage device according to an embodiment includes a drive circuit. A voltage applied to a dummy wire connected to a first dummy cell adjacent to a memory string is defined as a first dummy wire voltage, a voltage applied to a selection wire connected to a first memory cell adjacent to the first dummy cell is defined as a first selection wire voltage, and a voltage applied to a selection wire connected to a second memory cell adjacent to the first memory cell is defined as a second selection wire voltage. When the second selection wire voltage is lower than the first dummy wire voltage in an erase operation, the drive circuit controls voltages so that a difference between the first dummy wire voltage and the second selection wire voltage is less than a difference between the first dummy wire voltage and the first selection wire voltage.Type: ApplicationFiled: March 12, 2012Publication date: March 7, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHIINO, Eietsu Takahashi, Yuji Takeuchi
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Patent number: 8350309Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: December 2, 2011Date of Patent: January 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Patent number: 8344442Abstract: A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.Type: GrantFiled: February 3, 2012Date of Patent: January 1, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Yuji Takeuchi
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Patent number: 8316063Abstract: Provided is a technique for a data-driven database which frees a user from having to be conscious of a sequence in which instructions of a program for accessing a database are described, an interrelation of data items, and the like, and from having to describe redundant instructions. A data-driven database processor includes: schema definition storage means 2 for storing a schema definition of a database 24; derived definition storage means 3 for storing a derived definition describing a cause-and-effect relationship that exists when a value of a given data item is derived from a value of another data item; derived definition processing means 26 for generating a trigger program 27 that makes a chain of changes to values of data items based on the cause-and-effect relationship described in the derived definition; and a database management system 23 for executing the trigger program 27 when a change is made to the other data item that affects the value of the given data item.Type: GrantFiled: December 24, 2008Date of Patent: November 20, 2012Assignee: Rsun CorporationInventors: Ken Takeuchi, Yuji Takeuchi, Takahiro Yodo
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Publication number: 20120168846Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: March 15, 2012Publication date: July 5, 2012Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20120132980Abstract: A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.Type: ApplicationFiled: February 3, 2012Publication date: May 31, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yuji TAKEUCHI
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Patent number: 8167335Abstract: The present invention discloses a fender liner attached to a motor vehicle wheel house. The fender liner includes a breathable base material layer produced by forming a fiber assembly into a shape along the wheel house and a protective layer made of waterproof material. The protective layer is superimposed on a surface of the base material layer that is opposite to a side facing the wheel house. The protective layer is provided with a plurality of through-holes that allow air to flow through the protective layer to the surface of the base material layer on which the protective layer is superimposed.Type: GrantFiled: December 11, 2009Date of Patent: May 1, 2012Assignee: Hayashi Engineering Inc.Inventor: Yuji Takeuchi
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Publication number: 20120075903Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20120069672Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes a memory cell array. A control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write operation being an operation to apply a write pulse voltage to a selected memory cell and an intermediate voltage to an unselected memory cell. The control unit controls the step-up operation such that, in a first period, the intermediate voltage is maintained at a constant value, and, in a second period, the intermediate voltage is raised by a certain value. The control unit controls the step-up operation such that the first period includes an operation to raise the write pulse voltage by a first step-up value, and the second period includes an operation to raise the write pulse voltage by a second step-up value smaller than the first step-up value.Type: ApplicationFiled: June 27, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHIINO, Eietsu Takahashi, Yuji Takeuchi
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Patent number: 8134199Abstract: A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.Type: GrantFiled: November 2, 2010Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yuji Takeuchi
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Patent number: 8084802Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: GrantFiled: February 11, 2011Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Publication number: 20110210947Abstract: To provide an information processing apparatus having a user interface for enabling a user to readily give an instruction. A distance distribution image obtaining unit obtains a distance distribution image produced based a measured result output from a distance distribution measuring unit for measuring distance distribution to an object within a predetermined view field. An instruction content data producing unit produces instruction content data, based on the distance distribution image. An information processing execution unit obtains the instruction content data produced by the instruction content data producing unit, and carries out information processing based on the instruction content data.Type: ApplicationFiled: October 1, 2009Publication date: September 1, 2011Inventors: Satoshi Kawaguchi, Yuji Takeuchi
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Publication number: 20110186921Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20110134700Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.Type: ApplicationFiled: February 11, 2011Publication date: June 9, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira
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Patent number: 7939406Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: GrantFiled: May 5, 2009Date of Patent: May 10, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Michiharu Matsui, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20110042737Abstract: A nonvolatile semiconductor memory fabrication method including forming a first insulating film and a floating gate electrode material on a semiconductor substrate; forming a gate insulating film and a floating gate electrode by etching the first insulating film and the floating gate electrode material, respectively, and forming a groove for an element isolation region by etching the semiconductor substrate; and forming an element region and the element isolation region by burying a second insulating film in the groove and planarizing the second insulating film.Type: ApplicationFiled: November 2, 2010Publication date: February 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yuji TAKEUCHI