Patents by Inventor Yuji Tange

Yuji Tange has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8258472
    Abstract: A charged particle radiation device wherein the position or the size of a FOV can be easily determined even if a number of measuring points are provided on a sample, and an image capturing condition determining method using the charged particle radiation device are provided. An image capturing condition determining method wherein the field of view of a charged particle radiation device is determined so as to include a plurality of measuring points, characterized in that whether or not the measuring points are overlapped with four sides of the field of view is judged; the field of view is moved so that the measuring points are moved to the inside or outside of the field of view; and the position of the field of view after being moved is determined as a position of the field of view of the charged particle radiation device, and a device to realize the method are proposed.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 4, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tamotsu Shindo, Yuji Tange
  • Publication number: 20110260058
    Abstract: A charged particle radiation device wherein the position or the size of a FOV can be easily determined even if a number of measuring points are provided on a sample, and an image capturing condition determining method using the charged particle radiation device are provided. An image capturing condition determining method wherein the field of view of a charged particle radiation device is determined so as to include a plurality of measuring points, characterized in that whether or not the measuring points are overlapped with four sides of the field of view is judged; the field of view is moved so that the measuring points are moved to the inside or outside of the field of view; and the position of the field of view after being moved is determined as a position of the field of view of the charged particle radiation device, and a device to realize the method are proposed.
    Type: Application
    Filed: November 19, 2009
    Publication date: October 27, 2011
    Inventors: Tamotsu Shindo, Yuji Tange
  • Patent number: 6337486
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Publication number: 20010015413
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Application
    Filed: April 30, 2001
    Publication date: August 23, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6246064
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: June 12, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6127683
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: October 3, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 5972772
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: October 26, 1999
    Assignees: Hitachi Ltd., Hitachi Instruments Engineering Co., Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh