Patents by Inventor Yuji Torige
Yuji Torige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030257Abstract: Provided are an imaging device and a ranging device capable of reducing a chip size while suppressing diffraction of light to a light-shielding pixel region. The imaging device includes a semiconductor layer including an incident surface on which light is incident, a plurality of pixels provided on the semiconductor layer and arranged in parallel to the incident surface, and a reflection unit provided on the incident surface side of the semiconductor layer that reflects the light.Type: ApplicationFiled: November 10, 2021Publication date: January 25, 2024Inventors: YUJI TORIGE, HIRONOBU FUKUI
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Publication number: 20220239853Abstract: Provided is a technology capable of acquiring a saturation charge amount and improving low-light characteristics while suppressing an enlargement of a device and deterioration in pixel density.Type: ApplicationFiled: June 24, 2020Publication date: July 28, 2022Inventors: TAKUYA KURIHARA, YUJI TORIGE
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Patent number: 10902916Abstract: A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state.Type: GrantFiled: April 20, 2017Date of Patent: January 26, 2021Assignee: SONY CORPORATIONInventors: Yasuo Kanda, Yuji Torige
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Patent number: 10607700Abstract: A semiconductor circuit of the disclosure includes a first circuit that is able to generate, on the basis of a voltage at a first node, an inverted voltage of the voltage at the first node, and apply the inverted voltage to a second node, a second circuit that is able to generate, on the basis of a voltage at the second node, an inverted voltage of the voltage at the second node, and apply the inverted voltage to the first node, a first transistor that is turned ON to couple the first node to a third node, a second transistor that is turned ON to supply a first direct-current voltage to the third node, and a first storage section that is coupled to the third node and includes a first storage device that is able to take a first resistance state or a second resistance state.Type: GrantFiled: December 16, 2016Date of Patent: March 31, 2020Assignee: SONY CORPORATIONInventors: Yasuo Kanda, Yuji Torige
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Patent number: 10460805Abstract: A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.Type: GrantFiled: January 27, 2017Date of Patent: October 29, 2019Assignee: Sony CorporationInventors: Yasuo Kanda, Yuji Torige
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Publication number: 20190156891Abstract: A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state.Type: ApplicationFiled: April 20, 2017Publication date: May 23, 2019Inventors: YASUO KANDA, YUJI TORIGE
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Publication number: 20190051354Abstract: A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.Type: ApplicationFiled: January 27, 2017Publication date: February 14, 2019Applicant: SONY CORPORATIONInventors: Yasuo KANDA, Yuji TORIGE
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Publication number: 20190013076Abstract: A semiconductor circuit of the disclosure includes a first circuit that is able to generate, on the basis of a voltage at a first node, an inverted voltage of the voltage at the first node, and apply the inverted voltage to a second node, a second circuit that is able to generate, on the basis of a voltage at the second node, an inverted voltage of the voltage at the second node, and apply the inverted voltage to the first node, a first transistor that is turned ON to couple the first node to a third node, a second transistor that is turned ON to supply a first direct-current voltage to the third node, and a first storage section that is coupled to the third node and includes a first storage device that is able to take a first resistance state or a second resistance state.Type: ApplicationFiled: December 16, 2016Publication date: January 10, 2019Applicant: SONY CORPORATIONInventors: Yasuo KANDA, Yuji TORIGE
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Patent number: 9190166Abstract: A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.Type: GrantFiled: January 15, 2014Date of Patent: November 17, 2015Assignee: SONY CORPORATIONInventors: Yasuo Kanda, Koichi Amari, Shunsaku Tokitou, Yuji Torige, Takayuki Arima
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Patent number: 8953404Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.Type: GrantFiled: July 18, 2011Date of Patent: February 10, 2015Assignee: Sony CorporationInventors: Yasuo Kanda, Koichi Amari, Shunsaku Tokito, Yuji Torige, Takayuki Arima, Takafumi Kunihiro
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Publication number: 20140204649Abstract: A memory element includes: an electrical fuse provided to be inserted between a first input node and a second input node; and an antifuse provided to be inserted between the second input node and a third input node. The third input node is configured to be a node to which a voltage is allowed to be applied separately from a voltage to be applied to the first input node.Type: ApplicationFiled: January 15, 2014Publication date: July 24, 2014Applicant: Sony CorporationInventors: Yasuo Kanda, Koichi Amari, Shunsaku Tokitou, Yuji Torige, Takayuki Arima
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Patent number: 8760905Abstract: An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state of the second conductive layer.Type: GrantFiled: February 28, 2012Date of Patent: June 24, 2014Assignee: Sony CorporationInventors: Yasuo Kanda, Koichi Amari, Shunsaku Tokitou, Yuji Torige, Takayuki Arima
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Patent number: 8456884Abstract: Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array 1 has a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a flowing current and a plurality of cell transistors (TRB1 and TRB2) connected in parallel with respect to the fuse device F is arranged. In the relevant semiconductor device, out of the plurality of cell transistors (TRB1 and TRB2), the number of cell transistors turned ON is controllable by a writing control signal (WRITE) inputted from outside and an internal logic circuit 5 (and a word line drive circuit 4).Type: GrantFiled: June 8, 2010Date of Patent: June 4, 2013Assignee: Sony CorporationInventor: Yuji Torige
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Publication number: 20120243289Abstract: An electric fuse includes: a filament having a first conductive layer and a second conductive layer formed on the first conductive layer, wherein at least three discernible resistive states are generated in the filament by changing of a combination of a state of the first conductive layer and a state of the second conductive layer.Type: ApplicationFiled: February 28, 2012Publication date: September 27, 2012Applicant: SONY CORPORATIONInventors: Yasuo Kanda, Koichi Amari, Shunsaku Tokitou, Yuji Torige, Takayuki Arima
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Publication number: 20120039105Abstract: Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array 1 has a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a flowing current and a plurality of cell transistors (TRB1 and TRB2) connected in parallel with respect to the fuse device F is arranged. In the relevant semiconductor device, out of the plurality of cell transistors (TRB1 and TRB2), the number of cell transistors turned ON is controllable by a writing control signal (WRITE) inputted from outside and an internal logic circuit 5 (and a word line drive circuit 4).Type: ApplicationFiled: June 8, 2010Publication date: February 16, 2012Applicant: Sony CorporationInventor: Yuji Torige
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Publication number: 20120026822Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.Type: ApplicationFiled: July 18, 2011Publication date: February 2, 2012Applicant: SONY CORPORATIONInventors: Yasuo Kanda, Koichi Amari, Shunsaku Tokito, Yuji Torige, Takayuki Arima, Takafumi Kunihiro