Abstract: A differential amplifier stage under a band design whereby a data signal at a maximum transfer rate among received waveforms is subjected to attenuation upon passing through a transmission line is not amplified, and a signal at a transfer rate half the maximum transfer rate is amplified. If it is determined that a signal whose amplitude is larger in value than a high reference voltage, the signal is determined as a signal “1” while if smaller in value than a low reference voltage, the signal is determined as a signal “0”. If the first amplitude detector detects that the amplitude of the signal is smaller in value than the high reference voltage, and the second amplitude detector detects that the amplitude of the signal is larger in value than the low reference voltage, the present signal is determined as an inverting signal of an immediately preceding signal.

Abstract: In a receiving circuit, and in a semiconductor device and an information processing system including the receiving circuit, the receiving circuit is configured to amplify a high-speed signal by a greater gain than a low-speed signal with a low electric power consumption. The receiving circuit includes a first amplifier and a second amplifier having a cutoff frequency lower than a cutoff frequency of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, an output from the second amplifier is subtracted from an output from the first amplifier, and a result is outputted from the receiving circuit.

Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.

Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.

Abstract: A differential amplifier stage under a band design whereby a data signal at a maximum transfer rate among received waveforms is subjected to attenuation upon passing through a transmission line is not amplified, and a signal at a transfer rate half the maximum transfer rate is amplified. If it is determined that a signal whose amplitude is larger in value than a high reference voltage, the signal is determined as a signal “1” while if smaller in value than a low reference voltage, the signal is determined as a signal “0”. If the first amplitude detector detects that the amplitude of the signal is smaller in value than the high reference voltage, and the second amplitude detector detects that the amplitude of the signal is larger in value than the low reference voltage, the present signal is determined as an inverting signal of an immediately preceding signal.