Abstract: A low voltage differential signal driver includes an output driver including an N-channel source follower, a P-channel source follower, and a plurality of differential switching circuits, a plurality of high-potential output control circuits to control a terminal of the N-channel source follower of the output driver to make a high-potential output of the differential output from the output driver have a prescribed value, a plurality of low-potential output control circuits to control a terminal of the P-channel source follower of the output driver to make a low-potential output of the differential output from the output driver have a prescribed value, a high-potential generation circuit used in common for the plurality of high-potential output control circuits, and a low-potential generation circuit used in common for the plurality of low-potential output control circuits. The output driver outputs a differential output, and one of the plurality of high-potential output control circuits.

Abstract: A low voltage differential signal driver includes an output driver including an N-channel source follower, a P-channel source follower, and a plurality of differential switching circuits, a plurality of high-potential output control circuits to control a terminal of the N-channel source follower of the output driver to make a high-potential output of the differential output from the output driver have a prescribed value, a plurality of low-potential output control circuits to control a terminal of the P-channel source follower of the output driver to make a low-potential output of the differential output from the output driver have a prescribed value, a high-potential generation circuit used in common for the plurality of high-potential output control circuits, and a low-potential generation circuit used in common for the plurality of low-potential output control circuits. The output driver outputs a differential output, and one of the plurality of high-potential output control circuits.

Abstract: A low voltage differential signaling driver includes at least one output circuit, a first control circuit, and a second control circuit. The output circuit includes a first input terminal to receive a first input signal, a second input terminal to receive a second input signal, a first output terminal to output a first output signal, a second output terminal to output a second output signal, and first to sixth transistors. The first control circuit controls a voltage of a control terminal of the first transistor to make a voltage of the first output signal equal to a first reference voltage when the first input signal has a first value. The second control circuit controls a voltage of a control terminal of the second transistor to make the voltage of the first output signal equal to a second reference voltage when the first input signal has a second value.

Abstract: A low voltage differential signaling driver includes at least one output circuit, a first control circuit, and a second control circuit. The output circuit includes a first input terminal to receive a first input signal, a second input terminal to receive a second input signal, a first output terminal to output a first output signal, a second output terminal to output a second output signal, and first to sixth transistors. The first control circuit controls a voltage of a control terminal of the first transistor to make a voltage of the first output signal equal to a first reference voltage when the first input signal has a first value. The second control circuit controls a voltage of a control terminal of the second transistor to make the voltage of the first output signal equal to a second reference voltage when the first input signal has a second value.

Abstract: A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase.

Abstract: A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase.

Abstract: A testing circuit measures a center frequency of a clock signal outputted by a clock generator. The clock generator has a frequency modulator capable of (1) performing a frequency sampling accurately for the duration of modulation frequency and reducing the duration for frequency measurements, and (2) implementing proper testing of the down-spread controlling feature as one of the SSCG modulation functions by accurately determining the center frequency of the clock signal. The testing circuit measures a center frequency of a clock signal outputted by a clock generator by converting an analog modulation signal into a digital signal and outputting the digital signal, counting the period of the clock signal to obtain a count according to the digital signal outputted by the clock generator, and comparing the count with the predetermined specification values related to the center frequency of the clock signal to obtain and output a comparison result.

Abstract: A testing circuit configured to measure a center frequency of a clock signal outputted by a clock generator. The clock generator has frequency modulation capability of (1) performing a frequency sampling accurately for the duration of modulation frequency and reducing the duration for frequency measurements, and (2) implementing proper testing of the down-spread controlling feature as one of the SSCG modulation functions by accurately determining the center frequency of the clock signal. The testing circuit is configured to measure a center frequency of a clock signal outputted by a clock generator, by converting an analog modulation signal into a digital signal and outputting the digital signal, counting the period of the clock signal to obtain a count according to the digital signal outputted by the clock generator, and comparing the count with the predetermined specification values related to the center frequency of the clock signal to obtain a comparison result and outputting the comparison result.