Abstract: A defect pixel correction circuit that can easily determine a defect of an image sensor that has the defect that ranges to one direction and replace with the correcting pixel is provided. The defect pixel correction circuit 1 includes: a defect pixel determination unit 10 configured to determine whether a noteworthy pixel oo is a defect pixel referring to a referring pixels ko, mo, qo and so that excludes the noteworthy pixel oo, the referring pixels centering on the noteworthy pixel oo and lining up in one direction; and a defect pixel correcting unit 20 configured to generate a correcting pixel value on the basis of the referring pixels mo and qo, and replace the noteworthy pixel value that is pixel value of the noteworthy pixel oo with the correcting pixel value, when the noteworthy pixel oo is a defect pixel.

Abstract: A table value conversion device for use with a memory storing a default table value, a central processing unit for reading a default table value from the memory and outputting an output value, and a functional macro functioning as hardware for processing data and storing a lookup table. The device enables simple and efficient rewriting of values stored in the memory. The device includes a conversion module arranged on an external bus extending between the memory and the central processing unit. The conversion module receives the output value of the central processing unit, performs a correction computation on the received output value to generate a corrected value, and converts a table value of the lookup table in the functional macro based on the corrected value.

Abstract: An image processing system 1 comprises: a buffer 2 for storing a target pixel oo that is an object of image processing and a group of pixels surrounding the target pixel oo, such that the pixels are aligned in horizontal and vertical directions; a maximum value detector 31 for obtaining a maximum value Bmax from pixels of the surrounding pixel group which pixels have the same color as the target pixel oo; a minimum value detector 32 for obtaining a minimum value Bmin from the pixels of the surrounding pixel group which pixels have the same color as the target pixel oo; and a subtracter 33 for subtracting a result obtained by the minimum value detector 32 from a result obtained by the maximum value detector 31.

Abstract: A method for determining which one of regions in a chrominance space an input point belongs to. The regions are defined by boundary lines. The method includes generating in the chrominance space a first line, extending through the input point and the origin of the chrominance space, and a second line, connecting a point on the Cb axis of the chrominance space and a point on the Cr axis of the chrominance space. The method further includes comparing coordinates of a first intersection point, at which the first line and the second line intersect, and coordinates of second intersection points, at which the second line and the boundary lines intersect, to determine the region to which the input point belongs.

Abstract: An image processing circuit for eliminating noise from an image without lowering the actual resolution. The image contains input pixels, which include a processing subject pixel and proximal pixels located proximal to the processing subject pixel. Each input pixel has a pixel value. The image processing circuit includes a spatial filter for generating a filter value for the subject processing pixel based on the pixel values of the input pixels and first filter coefficients. A correction circuit compares the filter value with first and second limit values and corrects the filter value based on the comparison to generate a corrected filter value in a range between the first and second limit values. The image processing circuit eliminates noise from the image by correcting the pixel value of the processing subject pixel based on the corrected filter value.

Abstract: In designing a semiconductor device, a method of verifying an upper-hierarchy logic including a lower-hierarchy logic. First, a first verification logic having an output terminal, which is equivalent to an input terminal of the lower-hierarchy logic, and an input terminal, which is equivalent to an output terminal of the lower-hierarchy logic. Then, a second verification logic including only the input terminal and output terminal of the lower-hierarchy logic is produced, and an operational verification of the upper-hierarchy logic is executed using the first and second verification logics. This method eliminates the need for performing an operational verification of the lower-hierarchy logic at the time of the operational verification of the upper-hierarchy logic.

Abstract: In designing a semiconductor device, a method of verifying an upper-hierarchy logic including a lower-hierarchy logic. First, a first verification logic having an output terminal, which is equivalent to an input terminal of the lower-hierarchy logic, and an input terminal, which is equivalent to an output terminal of the lower-hierarchy logic. Then, a second verification logic including only the input terminal and output terminal of the lower-hierarchy logic is produced, and an operational verification of the upper-hierarchy logic is executed using the first and second verification logics. This method eliminates the need for performing an operational verification of the lower-hierarchy logic at the time of the operational verification of the upper-hierarchy logic.