Patents by Inventor Yuji Yukiiri
Yuji Yukiiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240155760Abstract: A method of making an interconnect substrate includes forming a first insulating layer containing a filler and covering a first interconnect layer, forming a via hole in the first insulating layer by laser processing, the via hole exposing the first interconnect layer, performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer, and forming, after the desmear process, a second interconnect layer including both an interconnect pattern formed on an upper surface of the first insulating layer and a via interconnect formed in the via hole.Type: ApplicationFiled: October 17, 2023Publication date: May 9, 2024Inventor: Yuji YUKIIRI
-
Patent number: 11617264Abstract: An interconnect substrate includes a first insulating layer, an interconnect layer formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, wherein both the first resin layer and the second resin layer contain a resin and a filler, and wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area.Type: GrantFiled: September 17, 2021Date of Patent: March 28, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Yuji Yukiiri
-
Publication number: 20220104352Abstract: An interconnect substrate includes a first insulating layer, an interconnect layer formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, wherein both the first resin layer and the second resin layer contain a resin and a filler, and wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area.Type: ApplicationFiled: September 17, 2021Publication date: March 31, 2022Inventor: Yuji YUKIIRI
-
Patent number: 10887985Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.Type: GrantFiled: March 29, 2019Date of Patent: January 5, 2021Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
-
Publication number: 20200120798Abstract: A wiring board includes: a core substrate having a through hole; an electrically conductive layer provided on a wall face of the through hole; and a filling material with which the through hole is filled and that contacts the electrically conductive layer. The filling material includes: a main portion that includes a resin and an inorganic filler; and a buffering portion that contacts the main portion and the electrically conductive layer and that includes at least a resin. A ratio of the inorganic filler contained in the main portion is higher than a ratio of an inorganic filler contained in the buffering portion, or the buffering portion does not include any inorganic filler.Type: ApplicationFiled: October 7, 2019Publication date: April 16, 2020Inventor: Yuji Yukiiri
-
Publication number: 20190230791Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventors: Natsuko KITAJO, Yuji YUKIIRI, Izumi TANAKA
-
Patent number: 10306759Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.Type: GrantFiled: December 18, 2017Date of Patent: May 28, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
-
Publication number: 20180184521Abstract: A wiring substrate includes a pad, an insulation layer that covers the pad, and a via wiring extending through the insulation layer and connected to the pad. The via wiring includes a first via portion, which has a diameter that is decreased from an upper surface of the insulation layer toward the pad, and a second via portion, which has a diameter that is increased from a lower end of the first via portion toward the pad. The diameter of the second via portion at an upper surface of the pad is larger than the diameter of the first via portion at the upper surface of the insulation layer.Type: ApplicationFiled: December 18, 2017Publication date: June 28, 2018Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
-
Patent number: 9711461Abstract: A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.Type: GrantFiled: October 20, 2016Date of Patent: July 18, 2017Assignee: Shinko Electric Industries Co., Ltd.Inventors: Natsuko Kitajo, Yuji Yukiiri, Izumi Tanaka
-
Publication number: 20170141044Abstract: A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.Type: ApplicationFiled: October 20, 2016Publication date: May 18, 2017Inventors: NATSUKO KITAJO, YUJI YUKIIRI, IZUMI TANAKA
-
Patent number: 8561293Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.Type: GrantFiled: April 26, 2012Date of Patent: October 22, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuji Yukiiri, Izumi Tanaka
-
Publication number: 20120204424Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.Type: ApplicationFiled: April 26, 2012Publication date: August 16, 2012Applicant: Shinko Electric Industries Co., Ltd.Inventors: Yuji YUKIIRI, Izumi Tanaka
-
Publication number: 20120144666Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.Type: ApplicationFiled: February 17, 2012Publication date: June 14, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yuji YUKIIRI, Izumi Tanaka
-
Patent number: 8196296Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.Type: GrantFiled: October 14, 2008Date of Patent: June 12, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuji Yukiiri, Izumi Tanaka
-
Patent number: 8129626Abstract: A multilayer wiring substrate having no core substrate is provided. The multilayer wiring substrate includes: a laminated body includes: a plurality of insulating layers; and a plurality of wiring layers. The laminated body has: a mounting surface on which a semiconductor element is mounted; and a bonding surface to which external connection terminals are bonded. At least one of the insulating layers contains a glass cloth.Type: GrantFiled: March 6, 2009Date of Patent: March 6, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Natsuko Ueda, Yuji Yukiiri
-
Patent number: 8034188Abstract: A method for cleaning a surface of a resin layer capable of sufficiently improving peel strength of a metal film formed by plating on a surface which is roughened by performing a desmear treatment on a resin layer containing a resin added with a large amount of filler is provided.Type: GrantFiled: December 6, 2006Date of Patent: October 11, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yoji Asahi, Yuji Yukiiri
-
Publication number: 20090236135Abstract: A multilayer wiring substrate having no core substrate is provided. The multilayer wiring substrate includes: a laminated body includes: a plurality of insulating layers; and a plurality of wiring layers. The laminated body has: a mounting surface on which a semiconductor element is mounted; and a bonding surface to which external connection terminals are bonded. At least one of the insulating layers contains a glass cloth.Type: ApplicationFiled: March 6, 2009Publication date: September 24, 2009Applicant: Shinko Electric Industries Co., Ltd.Inventors: Natsuko UEDA, Yuji YUKIIRI
-
Publication number: 20090100673Abstract: There is prepared an insulation layer generation member having a support film and a semi-cured insulation layer provided on a surface of the support film. Subsequently, the insulation layer generation member is affixed to a pad such that the pad contacts the semi-cured insulation layer. The semi-cured insulation layer is cured, to thus generate an insulation layer. Subsequently, the insulation layer is exposed to laser by way of the support film, thereby opening an opening in the insulation layer.Type: ApplicationFiled: October 14, 2008Publication date: April 23, 2009Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yuji YUKIIRI, Izumi TANAKA
-
Publication number: 20070131243Abstract: A method for cleaning a surface of a resin layer capable of sufficiently improving peel strength of a metal film formed by plating on a surface which is roughened by performing a desmear treatment on a resin layer containing a resin added with a large amount of filler is provided. The method is characterized in that, when a surface of a resin layer on which a metal film is formed by plating is roughened by a desmear treatment and, then, the thus-roughened surface of the resin layer is cleaned, the surface of the resin layer formed with a resin compounded with a filler in an amount of 20 wt % or more such that a difference of a coefficient of thermal expansion between the resin layer and the metal film is allowed to be reduced is roughened by subjecting it to the desmear treatment and, secondly, the filler which is deposited on the thus-roughened surface of the resin layer is removed by ultrasonic cleaning in which ultrasonic vibration of a frequency of from 35 to 50 kHz is applied.Type: ApplicationFiled: December 6, 2006Publication date: June 14, 2007Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yoji Asahi, Yuji Yukiiri