Abstract: The embodiment of the present disclosure discloses multimedia data processing method, apparatus, electronic device, and storage medium. The method comprises: displaying a first shooting page which includes a first icon; displaying identification information of one or more pieces of pre-buffered multimedia data according to an operation of a user on the first icon; acquiring a publishing instruction for target multimedia data of the one or more pieces of pre-buffered multimedia data according to the identification information; and in response to the publishing instruction, publishing the target multimedia data to a network. Due to the fact that the user usually enters the shooting page when wanting to share multimedia data through a terminal, therefore the user can see a draft browsing entrance more intuitively and publish a draft to the network by directly displaying the draft browsing entrance in the shooting page, and the probability of the draft being successfully published is increased.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

Abstract: The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).

Abstract: The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers.

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract: Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.

Abstract: The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

Abstract: The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal.

Abstract: A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching.

Abstract: Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.

Abstract: The present invention discloses a method for self-alignedly fabricating tunneling field-effect transistor (TFET) based on planar process, thereby lowering requirements on a photolithography process for fabricating the planar TFET. In the method, the source region and the drain region of the TFET are not directly defined by photolithography; rather, they are defined by another dielectric film which locates over an active region and on both sides of the gate and which is different from the dielectric film that defines the channel region. The influence due to the alignment deviation among three times of photolithography process for defining the channel region, the source and the drain regions may be eliminated by selectively removing the dielectric film over the source and drain regions by wet etching.