Abstract: A touch structure includes a touch functional layer and a first transparent layer. The touch functional layer includes a first conductive layer and a second conductive layer that are stacked. The first conductive layer includes a plurality of electrodes spaced apart from each other. Orthographic projections of the plurality of electrodes and a region between any two adjacent electrodes of the plurality of electrodes on a plane perpendicular to a thickness direction of the touch functional layer is within a range of an orthographic projection of the first transparent layer on the plane.

Abstract: The present disclosure provides a liquid crystal display panel and a display device, including: a liquid crystal panel, a light control panel, and a polarizer located on a surface of the liquid crystal panel away from the light control panel that are stacked, in which the polarizer includes a pressure-sensitive adhesive layer in contact with the liquid crystal panel, and the pressure-sensitive adhesive layer has a light adjustment structure configured to adjust a propagation path of light emitted from the liquid crystal panel by means of refraction or total reflection. The liquid crystal display panel provided by the present disclosure can improve or even eliminate the rainbow pattern phenomenon, and improve the display quality of the liquid crystal display panel.

Abstract: The present disclosure relates to a display panel and a display device. The display panel includes: a liquid crystal display panel; and a dimming liquid crystal panel including a plurality of dimming pixels defined by a second mesh structure and arranged in an array, wherein the second mesh structure includes a plurality of light shielding lines extending along a first direction and having a waveform, each of the light shielding lines includes a plurality of periodic parts, each of the plurality of periodic parts includes a first portion and a second portion which are symmetrical relative to a symmetry axis along a second direction, the first portion comprises a first segment and a second segment, the second portion comprises a third segment which is symmetrical with the second segment relative to the symmetry axis and a fourth segment which is symmetrical with the first segment relative to the symmetry axis.

Abstract: An overdrive method and device, a controller, a display apparatus, and a storage medium is provided. The method includes: acquiring a first grayscale value and a second grayscale value, the first grayscale value being a grayscale value of a first image displayed by a target sub-pixel and the second grayscale value being a grayscale of a second image to be displayed by the target sub-pixel; acquiring a hold duration that the target sub-pixel holds the first grayscale value in response to the first grayscale: value being not equal to the second grayscale value; determining a target overdrive compensation voltage according to the first grayscale value, the second grayscale value, and the hold duration; and applying an overdrive pixel voltage to the target sub-pixel in response to the target sub-pixel displaying the second image, the overdrive pixel voltage being obtained according to the target overdrive compensation voltage.

Abstract: A driving method of display panel, a display panel and a display device are disclosed. The driving method includes: in a single-frame display time, sequentially applying signals to a plurality of first sub-pixels connected to first data lines in a scanning direction so that: a signal polarity applied to each of a plurality of first white sub-pixels connected to first data lines is opposite to a signal polarity applied to a first sub-pixel which is located at an upstream of the first white sub-pixel along the scanning direction and is adjacent to the first white sub-pixel, and a signal polarity applied to each of a plurality of first colored sub-pixels is identical with a signal polarity applied to a first sub-pixel which is located at an upstream of the first colored sub-pixel along the scanning direction and is adjacent to the first colored sub-pixel.

Abstract: Embodiments of the present disclosure provide a pixel circuit. The pixel circuit includes a first transistor and a photosensitive component. A first end and a second end of the photosensitive component are connected to a gate line and a pixel electrode, respectively, and the photosensitive component is configured to transmit a signal of the gate line to the pixel electrode in response to receiving an external light signal. Embodiments of the present disclosure further provide a pixel unit including the pixel circuit as well as a display panel.

Abstract: Disclosed are a pixel array, a display panel and a display device. The pixel array includes: a plurality of pixel units arranged in an array, a plurality of data lines and a plurality of gate lines, wherein each of the pixel units includes four sub-pixel units; the first sub-pixel unit group includes two adjacent sub-pixel units, and the second sub-pixel unit group includes remaining two adjacent sub-pixel units; the first sub-pixel unit group and the second sub-pixel unit group are alternately arranged in both a row direction and a column direction; the data line connected with the two adjacent sub-pixel units included in the first sub-pixel unit group is different from the data line connected with the two adjacent sub-pixel units included in the second sub-pixel unit group.

Abstract: An array substrate, a display panel and a display device. The array substrate includes a base substrate including a plurality of pixel areas and a first data line on the base substrate and between adjacent pixel areas; a side slope angle of the first data line is not greater than about 60°.

Abstract: A display apparatus includes a backlight, and a plurality of display panels disposed over one another over one side of the backlight. Each display panel includes a plurality of pixel structures and a plurality of signal lines. It is configured such that orthographic projections of the plurality of pixel structures of each display panel on a plane perpendicular to a light transmission direction of the display apparatus substantially match with one another, and orthographic projections of the plurality of signal lines in at least two display panels on the plane cross with one another.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: Embodiments of the present disclosure provide a pixel circuit. The pixel circuit includes a first transistor and a photosensitive component. A first end and a second end of the photosensitive component are connected to a gate line and a pixel electrode, respectively, and the photosensitive component is configured to transmit a signal of the gate line to the pixel electrode in response to receiving an external light signal. Embodiments of the present disclosure further provide a pixel unit including the pixel circuit as well as a display panel.

Abstract: Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

Abstract: Disclosed are a pixel array, a display panel and a display device. The pixel array includes: a plurality of pixel units arranged in an array, a plurality of data lines and a plurality of gate lines, wherein each of the pixel units includes four sub-pixel units; the first sub-pixel unit group includes two adjacent sub-pixel units, and the second sub-pixel unit group includes remaining two adjacent sub-pixel units; the first sub-pixel unit group and the second sub-pixel unit group are alternately arranged in both a row direction and a column direction; the data line connected with the two adjacent sub-pixel units included in the first sub-pixel unit group is different from the data line connected with the two adjacent sub-pixel units included in the second sub-pixel unit group.

Abstract: A shift register unit, a driving method, and a gate driving circuit are disclosed. The shift register unit includes an input reset sub-circuit, which is connected to a first scan control terminal, a second scan control terminal, a first scan level terminal, a second scan level terminal and a pull-up node, respectively, and configured to control the pull-up node to connect with the first scan level terminal or the second scan level terminal under the control of a first scan control signal fed through the first scan control terminal and a second scan control signal fed through the second scan control terminal; a gate driving signal output sub-circuit; and a gate driving signal reset sub-circuit.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: A driving method of display panel, a display panel and a display device are disclosed. The driving method includes: in a single-frame display time, sequentially applying signals to a plurality of first sub-pixels connected to first data lines in a scanning direction so that: a signal polarity applied to each of a plurality of first white sub-pixels connected to the first data lines is opposite to a signal polarity applied to a first sub-pixel which is located at an upstream of the first white sub-pixel along the scanning direction and is adjacent to the first white sub-pixel, and a signal polarity applied to each of a plurality of first colored sub-pixels is identical with a signal polarity applied to a first sub-pixel which is located at an upstream of the first colored sub-pixel along the scanning direction and is adjacent to the first colored sub-pixel.

Abstract: Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

Abstract: An array substrate, a display panel and a display device. The array substrate includes a base substrate including a plurality of pixel areas and a first data line on the base substrate and between adjacent pixel areas; a side slope angle of the first data line is not greater than about 60°.

Abstract: Embodiments of the present disclosure provide an array substrate, a color filter substrate and a display panel. The array substrate includes: a base substrate; gate lines and data lines provided above the base substrate in a cross arrangement; and a plurality of pixel units defined by the gate lines and the data lines, each pixel unit including a pixel region and a non-pixel region. At least a portion of the gate line is located in the non-pixel region, a blocking wall region is formed in the non-pixel region and located between the portion of the gate line located in the non-pixel region and the pixel region, and a blocking wall structure for blocking movement of a spacer from the non-pixel region to the pixel region is formed in the blocking wall region.

Abstract: Embodiments of the disclosure disclose a gate driving circuit, a driving method, and a display device. In the gate driving circuit, the input module transmits the input signal of the input signal terminal to the first node. The reset module resets the first node and the output terminal of the gate driving circuit. The pull-down module pulls down the signal of the first node and the signal of the output terminal of the gate driving circuit to low level signals. The pull-down control module generates a voltage signal of the second node based on the signal of the noise-canceling signal terminal, and controls the pull-down module to pull down a high level noise signal at the first node to a low level signal using the voltage signal. The pull-up module pulls up the signal of the output terminal of the gate driving circuit to a high level signal.