Abstract: Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

Abstract: Disclosed are a pixel array, a display panel and a display device. The pixel array includes: a plurality of pixel units arranged in an array, a plurality of data lines and a plurality of gate lines, wherein each of the pixel units includes four sub-pixel units; the first sub-pixel unit group includes two adjacent sub-pixel units, and the second sub-pixel unit group includes remaining two adjacent sub-pixel units; the first sub-pixel unit group and the second sub-pixel unit group are alternately arranged in both a row direction and a column direction; the data line connected with the two adjacent sub-pixel units included in the first sub-pixel unit group is different from the data line connected with the two adjacent sub-pixel units included in the second sub-pixel unit group.

Abstract: A shift register unit, a driving method, and a gate driving circuit are disclosed. The shift register unit includes an input reset sub-circuit, which is connected to a first scan control terminal, a second scan control terminal, a first scan level terminal, a second scan level terminal and a pull-up node, respectively, and configured to control the pull-up node to connect with the first scan level terminal or the second scan level terminal under the control of a first scan control signal fed through the first scan control terminal and a second scan control signal fed through the second scan control terminal; a gate driving signal output sub-circuit; and a gate driving signal reset sub-circuit.

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

Abstract: Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.

Abstract: A driving method of display panel, a display panel and a display device are disclosed. The driving method includes: in a single-frame display time, sequentially applying signals to a plurality of first sub-pixels connected to first data lines in a scanning direction so that: a signal polarity applied to each of a plurality of first white sub-pixels connected to the first data lines is opposite to a signal polarity applied to a first sub-pixel which is located at an upstream of the first white sub-pixel along the scanning direction and is adjacent to the first white sub-pixel, and a signal polarity applied to each of a plurality of first colored sub-pixels is identical with a signal polarity applied to a first sub-pixel which is located at an upstream of the first colored sub-pixel along the scanning direction and is adjacent to the first colored sub-pixel.

Abstract: An array substrate, a display panel and a display device. The array substrate includes a base substrate including a plurality of pixel areas and a first data line on the base substrate and between adjacent pixel areas; a side slope angle of the first data line is not greater than about 60°.

Abstract: Embodiments of the present disclosure provide an array substrate, a color filter substrate and a display panel. The array substrate includes: a base substrate; gate lines and data lines provided above the base substrate in a cross arrangement; and a plurality of pixel units defined by the gate lines and the data lines, each pixel unit including a pixel region and a non-pixel region. At least a portion of the gate line is located in the non-pixel region, a blocking wall region is formed in the non-pixel region and located between the portion of the gate line located in the non-pixel region and the pixel region, and a blocking wall structure for blocking movement of a spacer from the non-pixel region to the pixel region is formed in the blocking wall region.

Abstract: Embodiments of the disclosure disclose a gate driving circuit, a driving method, and a display device. In the gate driving circuit, the input module transmits the input signal of the input signal terminal to the first node. The reset module resets the first node and the output terminal of the gate driving circuit. The pull-down module pulls down the signal of the first node and the signal of the output terminal of the gate driving circuit to low level signals. The pull-down control module generates a voltage signal of the second node based on the signal of the noise-canceling signal terminal, and controls the pull-down module to pull down a high level noise signal at the first node to a low level signal using the voltage signal. The pull-up module pulls up the signal of the output terminal of the gate driving circuit to a high level signal.

Abstract: The present invention provides an array substrate and a display device, to solve the problem of low testing precision due to significant difference between characteristics of TFTs in the detecting region and TFTs in the display region in the prior art. The array substrate comprises a display region and a dummy pixel region provided in the periphery of the display region, wherein, at least one detecting unit is provided in the dummy pixel region, each detecting unit comprises one second pixel unit, one thin film transistor is provided correspondingly to each second pixel unit, and respective electrodes of each thin film transistor provided correspondingly to the second pixel unit are connected to an external test device through test lines, respectively.

Abstract: A method and system for resynchronizing an embedded multimedia system using bytes consumed in an audio decoder. The bytes consumed provides a mechanism to compensate for bit error handling and correction in a system that does not require re-transmission. The audio decoder keeps track of the bytes consumed and periodically reports the bytes consumed. A host microprocessor indexes the actual bytes consumed since bit errors may have been handled or corrected to a predetermined byte count to determine whether resynchronization is necessary.

Abstract: A method and system for resynchronizing an embedded multimedia system using bytes consumed in an audio decoder. The bytes consumed provides a mechanism to compensate for bit error handling and correction in a system that does not require re-transmission. The audio decoder keeps track of the bytes consumed and periodically reports the bytes consumed. A host microprocessor indexes the actual bytes consumed since bit errors may have been handled or corrected to a predetermined byte count to determine whether resynchronization is necessary.