Patents by Inventor Yujie Liu

Yujie Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200219936
    Abstract: The present disclosure discloses a color film assembly, a display substrate and a method for fabricating the same, and a display apparatus. The color film assembly includes a quantum dot layer, and a filter layer on a light emitting side of the quantum dot layer. The filter layer includes filter units. Each of the filter units includes a first filter structure. A light emitting surface of the first filter structure has at least one converging structure. The quantum dot layer includes quantum dot units which are in one-to-one correspondence with the filter units. Each quantum dot unit includes at least one quantum dot structure. The quantum dot structures in each quantum dot unit are in one-to-one correspondence with the first filter structures in the corresponding filter unit.
    Type: Application
    Filed: November 15, 2019
    Publication date: July 9, 2020
    Inventors: Jiahui Han, Zheng Fang, Ming Zhu, Ge Shi, Haijun Niu, Shiyu Zhang, Yujie Liu, Song Yang, Yuyao Wang
  • Publication number: 20200150134
    Abstract: This disclosure provides a gene chip comprising a substrate and at least one positioning device fixed on an upper surface of the substrate, wherein the at least one positioning device is provided with a receiving cavity for receiving a bead, the receiving cavity being arranged on a surface of the at least one positioning device facing away from the substrate, and a cross-sectional area of the receiving cavity is gradually decreased in a direction toward the upper surface of the substrate. This disclosure further provides a gene detection device comprising the gene chip.
    Type: Application
    Filed: June 24, 2019
    Publication date: May 14, 2020
    Inventors: Song YANG, Ming ZHU, Shiyu ZHANG, Jiahui HAN, Zheng FANG, Ge SHI, Haijun NIU, Yujie LIU, Yuyao WANG
  • Publication number: 20200117044
    Abstract: Disclosed are a display substrate and a method for manufacturing the same, a display panel and a display device. The display panel includes a carrier substrate; an adhesive layer, a color resist layer, a first flat layer and a metal wire grid layer that are distributed in a direction distal from the carrier substrate; and a light shielding pattern disposed between the adhesive layer and the first flat layer. A surface of the light shielding pattern proximal to the metal wire grid layer is in the same plane as a surface of the color resist layer proximal to the metal wire grid layer. The present disclosure contributes to increasing the yield of the metal wire grid layer and improving the display effect of the display panel.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 16, 2020
    Inventors: Zheng Fang, Ge Shi, Ming Zhu, Haijun Niu, Shiyu Zhang, Song Yang, Yujie Liu, Jiahui Han, Yuyao Wang
  • Publication number: 20200089044
    Abstract: The disclosure discloses a display panel and a display device. The display panel includes: a base substrate, a reflecting layer, a dielectric grating layer, a filter layer, and a color filter layer including a first color filter element for transmitting light rays in a first color, a second color filter element for transmitting light rays in a second color, and a third color filter element for transmitting white light; the filter layer is configured to transmit light rays in first and second colors, and to reflect light rays in a third color; the dielectric grating layer includes a grating element corresponding in position to the third color filter element, and configured to reflect light rays in the first color transmitted through the filter layer to the first color filter element, and to reflect light rays in the second color transmitted through the filter layer to the second color filter element.
    Type: Application
    Filed: June 20, 2019
    Publication date: March 19, 2020
    Inventors: Yujie LIU, Ming ZHU, Song YANG, Haijun NIU, Zheng FANG, Ge SHI, Shiyu ZHANG, Jiahui HAN, Yuyao WANG
  • Publication number: 20200088921
    Abstract: Disclosed are a color filter substrate, a method for fabricating the same, and a display device. The color filter substrate includes a plurality of color-resist elements, and the color filter substrate further includes: a base substrate, and a groove arranged on the base substrate in correspondence to each of the color-resist elements, wherein a size of an opening of each groove is increase from the bottom to the top, a reflecting layer is coated on an inner surface of the groove, and a color-resist filler corresponding to a color of light emitted by the color-resist element is further filled in the groove above the reflecting layer.
    Type: Application
    Filed: June 21, 2019
    Publication date: March 19, 2020
    Inventors: Song YANG, Ge SHI, Ming ZHU, Shiyu ZHANG, Zheng FANG, Haijun NIU, Yujie LIU, Jiahui HAN, Yuyao WANG
  • Publication number: 20200073167
    Abstract: A display substrate, a method for manufacturing the same, and a display device are provided. The display substrate includes a base substrate, a black matrix pattern on the base substrate, display units respectively in regions defined by the black matrix pattern, and a light-reflecting wall between at least two adjacent display units, where at least one of the at least two adjacent display units is a quantum dot display unit, and a reflectance of the light-reflecting wall to light in a first wavelength range is greater than a preset threshold.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 5, 2020
    Inventors: Ge Shi, Shiyu Zhang, Mlng Zhu, Haijun Niu, Yujie Liu, Zheng Fang, Yuyao Wang, Xiaochuan Chen
  • Publication number: 20190392754
    Abstract: The present application provides a driving method of a display panel, a computer storage medium, a compensation circuit, and a display device. The display panel includes a plurality of sub-pixels, each of the plurality of sub-pixels including a pixel electrode and a common electrode, the driving method including: determining a data signal to be provided to the pixel electrode of each of the plurality of sub-pixels according to an image to be displayed by the display panel; calculating a compensation data signal to be provided to the pixel electrode of each of the plurality of sub-pixels according to the data signal; and providing the data signal and the compensation data signal simultaneously to the pixel electrode of each of the plurality of sub-pixels.
    Type: Application
    Filed: May 15, 2019
    Publication date: December 26, 2019
    Inventors: Meiling JIN, Tingting ZHAO, Zhengju JIN, Liangliang LI, Yingxue YU, Linshuo GU, Yujie LIU, Qin XIN, Cai ZHENG, Yahui NIU, Lulu LI
  • Patent number: 9727369
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: August 8, 2017
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Publication number: 20160259663
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Application
    Filed: May 16, 2016
    Publication date: September 8, 2016
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Patent number: 9368624
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: June 14, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 9342380
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 17, 2016
    Assignee: Oracle International Corporation
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Patent number: 9196727
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 24, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Publication number: 20150333144
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 9041126
    Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim
  • Publication number: 20150061012
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Patent number: 8883600
    Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 11, 2014
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane
  • Publication number: 20140258645
    Abstract: Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 11, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: David Dice, Yosef Lev, Yujie Liu, Victor M. Luchangco, Mark S. Moir
  • Publication number: 20140084385
    Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 27, 2014
    Applicant: SuVolta, Inc.
    Inventors: Thomas Hoffmann, Lucian Shifren, Scott E. Thompson, Pushkar Ranade, Jing Wang, Paul E. Gregory, Sachin R. Sonkusale, Lance Scudder, Dalong Zhao, Teymur Bakhishev, Yujie Liu, Lingquan Wang, Weimin Zhang, Sameer Pradhan, Michael Duane, Sung Hwan Kim
  • Publication number: 20080272394
    Abstract: Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.
    Type: Application
    Filed: October 10, 2007
    Publication date: November 6, 2008
    Inventors: Ashok Kumar Kapoor, Madhukar B. Vora, Weimin Zhang, Sachin R. Sonkusale, Yujie Liu