Patents by Inventor Yu-jin Seo

Yu-jin Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250089418
    Abstract: A display device and a method of manufacturing a display device are disclosed. A display device includes a planarization layer including a first planarization part on a substrate, and a second planarization part and a third planarization part on the first planarization part, a first pad electrode on the second planarization part, and a second pad electrode on the third planarization part, an organic pattern layer on the first pad electrode and the second pad electrode, a light emitting element on the organic pattern layer, a partition wall, a reflective layer on a side of the partition wall and the first planarization part, a first auxiliary connection electrode connecting the second semiconductor layer and the first pad electrode, and a second auxiliary connection electrode connecting the first semiconductor layer and the second pad electrode, and the planarization layer has an undercut shape.
    Type: Application
    Filed: August 27, 2024
    Publication date: March 13, 2025
    Inventors: Ki Chang EOM, Gwang Geun LEE, Ki Seong SEO, Yu Jin LEE, Jung An LEE
  • Publication number: 20250089408
    Abstract: The present disclosure may provide a display device and a method for manufacturing the same. According to one or more embodiments, a display device includes a pixel electrode above a substrate, a light-emitting element above the pixel electrode, and including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer in sequence, the third semiconductor layer defining a recess exposing a portion of the second semiconductor layer, a via layer above the substrate, and surrounding at least a portion of the light-emitting element, and a common electrode above the light-emitting element and the via layer, and directly contacting the second semiconductor layer through the recess.
    Type: Application
    Filed: August 29, 2024
    Publication date: March 13, 2025
    Inventors: Jung An LEE, Gwang Geun LEE, Ki Seong SEO, Ki Chang EOM, Yu Jin LEE
  • Publication number: 20250081681
    Abstract: A display device includes a pixel electrode on a substrate, a bank layer on the substrate and the pixel electrode and dividing a light emitting area and a light non-emitting area, light emitting elements on the pixel electrode and including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and second semiconductor layers, a first via layer on the pixel electrode and around sides of the light emitting elements, a common electrode on the first via layer, a side of a light emitting element protruding from the first via layer, and a top surface of the light emitting element, a first insulating layer on the common electrode, a partition wall unit on the first insulating layer and overlapping the bank layer, a second insulating layer on the partition wall unit, and a reflective layer around a side of the partition wall unit.
    Type: Application
    Filed: August 22, 2024
    Publication date: March 6, 2025
    Inventors: Ki Seong SEO, Min Chul SHIN, Ki Chang EOM, So Yeon YOON, Gwang Geun LEE, Yu Jin LEE, Jung An LEE
  • Publication number: 20250079411
    Abstract: A display device includes a planarization layer including a first planarization unit on a substrate and a second planarization unit on the first planarization unit, a pixel electrode on the second planarization unit, an organic pattern layer on the pixel electrode, a light emitting element on the organic pattern layer and having a downwardly convex recess on a top surface thereof, a first partition wall on one surface of the first planarization unit and forming a space around the light emitting element, a via layer in the space around the light emitting element, a first reflective layer around a side of the first partition wall in the space around the light emitting element, on the first planarization unit, and around a side of the light emitting element, a side of the organic pattern layer, and a side of the pixel electrode.
    Type: Application
    Filed: August 20, 2024
    Publication date: March 6, 2025
    Inventors: Yu Jin LEE, Gwang Geun LEE, Ki Seong SEO, Ki Chang EOM, Jung An LEE
  • Publication number: 20250055969
    Abstract: An image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jeong Eun SONG, Oh Jun KWON, Yu Jin PARK, Sung Uk SEO, Min Seok SHIN, Sun Young LEE
  • Publication number: 20250055968
    Abstract: An image sensing device includes a first sampling circuit suitable for sampling a reference ramp signal as a ramp signal; a switching circuit suitable for sequentially outputting first and second pixel signals to a common node based on first and second control signals; a second sampling circuit suitable for sampling the first and second pixel signals, which are sequentially outputted through the common node, as a measurement signal; a comparison circuit suitable for comparing the ramp signal with the measurement signal and generating a comparison signal corresponding to a comparison result; and a count circuit suitable for generating a count signal, which corresponds to a voltage level of the measurement signal, based on the comparison signal and a clock signal.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Inventors: Jeong Eun SONG, Oh Jun KWON, Yu Jin PARK, Sung Uk SEO, Min Seok SHIN, Sun Young LEE
  • Patent number: 11812609
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Yu Jin Seo, Jun Eon Jin
  • Publication number: 20230174465
    Abstract: The present specification relates to a compound as a UBR box domain ligand. The present specification provides a small molecule compound that binds to the UBR box domain. Further, the present specification provides a composition for inhibiting UBR box domain substrate binding, including a ligand compound that binds to a UBR box domain, a pharmaceutical composition for treating UBR-related disease, and a use thereof.
    Type: Application
    Filed: April 27, 2021
    Publication date: June 8, 2023
    Inventors: Yong Tae KWON, Hyun Tae KIM, Jeong Eun NA, Yu Jin SEO, Chang Hoon JI, Ha Rim CHOI, Ji Eun LEE, Ah Jung HEO
  • Publication number: 20230174470
    Abstract: The present specification relates to a compound as a UBR box domain ligand. The present specification provides a small molecule compound that binds to the UBR box domain. Further, the present specification provides a composition for inhibiting UBR box domain substrate binding, including a ligand compound that binds to a UBR box domain, a pharmaceutical composition for treating UBR-related disease, and a use thereof.
    Type: Application
    Filed: April 27, 2021
    Publication date: June 8, 2023
    Inventors: Yong Tae KWON, Hyun Tae KIM, Jeong Eun NA, Yu Jin SEO, Chang Hoon JI, Ha Rim CHOI, Ji Eun LEE, Ah Jung HEO
  • Publication number: 20220032300
    Abstract: A multiplex PCR chip capable of simultaneously detecting multiple target genes and a multiplex PCR method using the same are proposed. More specifically, in the multiplex PCR chip and multiplex PCR method, after a plurality of spatially separated particle-forming grooves is formed in one or more reaction chambers and a probe in a solution state is injected into the particle-forming grooves, planar shapes of the particle-forming grooves are varied or shapes and patterns of particle holders respectively formed on inner surfaces of the particle-forming grooves are varied, and the probe including primers specifically hybridizing with sequences of different nucleic acid molecules is injected into the particle-forming grooves, whereby simultaneous multiplex detection is possible by allowing multiple target genes to be detected on the basis of positions and shapes of the probe particles and the shapes and patterns of the particle holders respectively formed inside of the probe particles.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Applicant: Genesystem Co., Ltd.
    Inventors: Yu Jin SEO, Ok Ran CHOI, Dobu LEE, Ji Young PARK
  • Publication number: 20210242229
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Application
    Filed: March 31, 2021
    Publication date: August 5, 2021
    Inventors: BYOUNG IL LEE, Yu Jin Seo, Jun Eon Jin
  • Patent number: 11004866
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung il Lee, Jun Ho Cha
  • Patent number: 10998327
    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Bin Kang, Byoung Il Lee, Ji Mo Gu, Yu Jin Seo, Tak Lee
  • Patent number: 10978465
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Yu Jin Seo, Jun Eon Jin
  • Publication number: 20200185412
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: TAK LEE, SU BIN KANG, JI MO GU, YU JIN SEO, BYOUNG iL LEE, JUN HO CHA
  • Patent number: 10566346
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung Il Lee, Jun Ho Cha
  • Publication number: 20190355737
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 21, 2019
    Inventors: BYOUNG IL LEE, YU JIN SEO, JUN EON JIN
  • Publication number: 20190355736
    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 21, 2019
    Inventors: SU BIN KANG, Byoung Il Lee, Ji Mo Gu, Yu Jin Seo, Tak Lee
  • Publication number: 20190244969
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Application
    Filed: August 22, 2018
    Publication date: August 8, 2019
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung Il Lee, Jun Ho Cha
  • Publication number: 20180175143
    Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 21, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chan-sic YOON, Ki-seok Lee, Ki-wook Jung, Dong-oh Kim, Ho-in Lee, Je-min Park, Seok-han Park, Augustin Hong, Ju-yeon Jang, Hyeon-ok Jung, Yu-jin Seo