Patents by Inventor Yujin TERASAWA

Yujin TERASAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11778818
    Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: October 3, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ryo Mochizuki, Yasuo Kasagi, Michiaki Sano, Junji Oh, Yujin Terasawa, Hiroaki Namba
  • Publication number: 20230223266
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Fei ZHOU, Rahul SHARANGPANI, Raghuveer S. MAKALA, Yujin TERASAWA, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Masaaki HIGASHITANI
  • Publication number: 20230223267
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Rahul SHARANGPANI, Fei ZHOU, Raghuveer S. MAKALA, Yujin TERASAWA, Naoki TAKEGUCHI, Kensuke YAMAGUCHI
  • Publication number: 20230223248
    Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventors: Fei ZHOU, Rahul SHARANGPANI, Raghuveer S. MAKALA, Yujin TERASAWA, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Masaaki HIGASHITANI
  • Patent number: 11532570
    Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: December 20, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Genta Mizuno, Kenzo Iizuka, Satoshi Shimizu, Keisuke Izumi, Tatsuya Hinoue, Yujin Terasawa, Seiji Shimabukuro, Ryousuke Itou, Yanli Zhang, Johann Alsmeier, Yusuke Yoshida
  • Publication number: 20220352199
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
    Type: Application
    Filed: November 10, 2021
    Publication date: November 3, 2022
    Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
  • Publication number: 20220352200
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
    Type: Application
    Filed: November 10, 2021
    Publication date: November 3, 2022
    Inventors: Michiaki SANO, Yusuke MUKAE, Naoki TAKEGUCHI, Yujin TERASAWA, Tatsuya HINOUE, Ramy Nashed Bassely SAID
  • Publication number: 20220254733
    Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Inventors: Genta MIZUNO, Kenzo IIZUKA, Satoshi SHIMIZU, Keisuke IZUMI, Tatsuya HINOUE, Yujin TERASAWA, Seiji SHIMABUKURO, Ryousuke ITOU, Yanli ZHANG, Johann ALSMEIER, Yusuke YOSHIDA
  • Publication number: 20220028879
    Abstract: An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: Ryo MOCHIZUKI, Yasuo KASAGI, Michiaki SANO, Junji OH, Yujin TERASAWA, Hiroaki NAMBA
  • Patent number: 10916504
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yusuke Mukae, Naoki Takeguchi, Kensuke Yamaguchi, Raghuveer S. Makala, Yujin Terasawa
  • Publication number: 20200395310
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Yusuke MUKAE, Naoki TAKEGUCHI, Kensuke YAMAGUCHI, Raghuveer S. MAKALA, Yujin TERASAWA
  • Patent number: 10608010
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 31, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yujin Terasawa, Genta Mizuno, Yusuke Mukae, Yoshinobu Tanaka, Shiori Kataoka, Ryosuke Itou, Kensuke Yamaguchi, Naoki Takeguchi
  • Publication number: 20190280001
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.
    Type: Application
    Filed: June 7, 2018
    Publication date: September 12, 2019
    Inventors: Yujin TERASAWA, Genta MIZUNO, Yusuke MUKAE, Yoshinobu TANAKA, Shiori KATAOKA, Ryosuke ITOU, Kensuke YAMAGUCHI, Naoki TAKEGUCHI