Abstract: A display substrate and a display apparatus. The display substrate includes multiple circuit units, a circuit unit at least includes a pixel drive circuit, the pixel drive circuit at least includes a second transistor, a third transistor, a fourth transistor and a ninth transistor, a gate electrode of the third transistor is connected to a second electrode of the ninth transistor, a first electrode of the third transistor is connected to a second electrode of the fourth transistor, a second electrode of the third transistor is connected to a second electrode of the second transistor, and a first electrode of the second transistor is connected to a first electrode of the ninth transistor; the second transistor and the ninth transistor are configured such that a moment when the ninth transistor is turned off is earlier than a moment when the second transistor is turned off in the data writing stage.

Abstract: A display substrate including a base substrate, a bottom metal layer (10) and a gate drive circuit. The base substrate includes a display region (AA), and a peripheral region (BB) located at a periphery of the display region (AA). A bottom metal layer (10) and a gate drive circuit are located in the peripheral region (BB), and the bottom metal layer (10) is electrically connected with at least one kind of signal lines. The gate drive circuit is located on one side of the bottom metal layer (10) away from the base substrate. The gate drive circuit includes a plurality of first circuit units. An orthographic projection of the bottom metal layer (10) on the base substrate is at least partially overlapped with an orthographic projection of at least one first circuit unit on the base substrate.

Abstract: A layer composition method, a terminal device, and a storage medium, related to the field of terminal technologies, are provided. In the embodiments, in a process in which a user uses a large screen, the terminal device may recognize each to-be-composed layer, to determine whether the layer needs to be preprocessed by using a GPU, such as wallpaper layer rotation. If preprocessing needs to be performed by using the GPU, a preprocessed layer is rendered by using the GPU, and the preprocessed layer is stored into a buffer. When a same layer processing task exists subsequently, the preprocessed layer in the buffer can be directly sent to an HWC for hardware composition, without using GPU composition, thereby reducing overall power consumption and load of the terminal device and improving overall performance.

Abstract: A display substrate includes a base substrate, a scan line and a driving module arranged on the base substrate, at least two transistors in the driving circuit have a first gate electrode and a second gate electrode; at least a portion of the second gate electrode is located between the first gate electrode and the base substrate; bottom gate via holes of at least two transistors of the driving circuit are arranged along a first direction; the second gate electrode is electrically connected to a connection portion through the bottom gate via hole, and the connection portion is electrically connected to the first gate electrode; or, the second gate electrode is electrically connected to the first gate electrode through the bottom gate via hole; the first direction intersects with a second direction, and the scan line includes at least a portion extending along the second direction.

Abstract: A display panel, including: a base substrate including a display region and a peripheral region, wherein the display region includes an outer boundary; a first electrode layer, a pixel defining layer and a photo spacer layer sequentially arranged on the base substrate. The display panel further includes at least one barrier dam arranged on the base substrate, which is located on a side of the peripheral region away from the display region in the peripheral region. The photo spacer layer includes a plurality of first photo spacers and second photo spacers respectively arranged in an array in the display region and the peripheral region, and the second photo spacer is located between the outer boundary and the at least one barrier dam. A distribution density of the second photo spacers in the peripheral region is less than that of the first photo spacers in the display region.

Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate, including a display region and a bonding region located around the display region; a plurality of first pixel driving circuits located on the base substrate; a plurality of first data lines; and a plurality of first leads, the display region includes a first region and a second region located at a side of the first region, and the plurality of first pixel driving circuits are located in the second region, the plurality of first data lines are located in a layer different from a layer where the plurality of first leads are located.

Abstract: A display panel including: a base substrate including a display region and a peripheral region, wherein the display region includes an outer boundary; a first electrode layer, a pixel defining layer and a photo spacer layer sequentially arranged on the base substrate. The display panel further includes at least one barrier dam arranged on the base substrate, which is located on a side of the peripheral region away from the display region in the peripheral region. The photo spacer layer includes a plurality of first photo spacers and second photo spacers respectively arranged in an array in the display region and the peripheral region, and the second photo spacer is located between the outer boundary and the at least one barrier dam. A distribution density of the second photo spacers in the peripheral region is less than that of the first photo spacers in the display region.

Abstract: An array substrate is provided. The array substrate includes a plurality of first type data lines and a plurality of second type data lines. A respective one of the plurality of first type data lines crosses over subpixel apertures of multiple subpixels of a first color, and does not crosses over subpixel apertures of any subpixel of a second color and does not crosses over subpixel apertures of any subpixel of a third color, the first color, the second color, and the third color being different colors. A respective one of the plurality of second type data line does not cross over any subpixel aperture. A respective subpixel aperture of a subpixel of the first color includes a first region and a second region. A ratio of a first area of the first region to a second area of the second region is in a range of 2:8 to 8:2.

Abstract: A display substrate, comprising: a base and multiple first lead-out signal lines. The base comprises a display area and a peripheral area surrounding the display area; and the peripheral area comprises a first bezel area located on one side of the display area. The multiple first lead-out signal lines are located in the first bezel area. At least one of the multiple first lead-out signal lines comprises: a first trace, a second trace, and a third trace that are stacked; and the second trace is electrically connected to the first trace and the third trace. The orthographic projection of the first trace on the base, the orthographic projection of the second trace on the base, and the orthographic projection of the third trace on the base at least partially overlap each other.

Abstract: An array substrate and a display device are disclosed. In the array substrate, the base substrate includes a display region and a bonding region; the display region includes a first region and a second region, and the plurality of first pixel driving circuits are located in the second region, the plurality of first pixel driving circuits are arranged in an array along a first direction and a second direction to form a plurality of first pixel driving columns arranged along the first direction, the first region and the second region are arranged in the first direction, the plurality of first data lines are configured to provide data signals to the plurality of first pixel driving columns, and the plurality of first leads are respectively connected with the plurality of first data lines, and at least partially located in the first region and the second region.

Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes multiple pixel circuits arranged in an array and located in the display region and multiple drive circuits located in the non-display region. At least one pixel circuit includes multiple transistors and the multiple drive circuits are configured to provide drive signals to the multiple transistors; the circuit structure layer further includes: a high-level power supply line and a low-level power supply line located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line and the low-level power supply line respectively, and the high-level power supply line and the low-level power supply line extend along a first direction.

Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes multiple pixel circuits arranged in an array and located in the display region and multiple drive circuits located in the non-display region. At least one pixel circuit includes multiple transistors and the multiple drive circuits are configured to provide drive signals to the multiple transistors; the circuit structure layer further includes: a high-level power supply line and a low-level power supply line located in the non-display region, at least one drive circuit is electrically connected with the high-level power supply line and the low-level power supply line respectively, and the high-level power supply line and the low-level power supply line extend along a first direction.

Abstract: A display panel includes: a light emitting unit; a base substrate, including a light transmitting area; a light shielding layer, located on a side of the base substrate and configured with a light shielding function; a pixel defining layer, located on a side of the light shielding layer away from the base substrate, wherein a pixel opening is formed on the pixel defining layer, and the light emitting unit is formed in the pixel opening; and multiple functional layers, located between the base substrate and the pixel defining layer, and orthographic projections, on the base substrate, of light shielding structures of the multiple functional layers are located outside the light transmitting area; wherein a first opening is formed on the light shielding layer, and an orthographic projection of the first opening on the base substrate is located in the light transmitting area.

Abstract: An array substrate includes a substrate, data lines, fan-out leads, first dummy lines an second dummy lines. A fan-out lead includes a first lead and a second lead. The first lead extends from a lead-out region to a first wiring region. An end of the second lead is electrically connected to the first lead, and another end of the second lead is electrically connected to one data line. The first dummy lines are disposed in first wiring regions and located on a side, away from the lead-out region, of all first leads as a whole. A part of the second dummy lines is located in a second wiring region where no second lead is arranged; and another part of the second dummy lines is located in the second wiring region where the second lead is arranged and is located on at least one side of the second lead.

Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate, including a display region and a bonding region located around the display region; a plurality of first pixel driving circuits located on the base substrate; a plurality of first data lines; and a plurality of first leads, the display region includes a first region and a second region located at a side of the first region, and the plurality of first pixel driving circuits are located in the second region, the plurality of first data lines are located in a layer different from a layer where the plurality of first leads are located.

Abstract: A measurement method for the impedance of the converter at multiple operating points based on the secondary-side disturbance includes the following steps: superimposing the positive sequence current disturbance in the current sampling value; superimposing the positive sequence voltage disturbance in the voltage sampling value; determining whether measurement data of the converter at two or more current operating points are obtained, if so, based on the measurement data of the converter at two current operating points, calculating values of A(s) and B(s); further calculating values of coefficients at each frequency point, and obtaining the impedance value of the converter at multiple current operating points by calculation. The above-mentioned measurement method overcomes the disadvantages of high cost and complicated operation of the impedance measurement method based on the primary-side disturbance, and solves the problem of lacking the pre-judgment function.

Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a display region and a non-display region, the display substrate includes a base substrate and a circuit structure layer disposed on the base substrate, the circuit structure layer includes multiple pixel circuits arranged in an array and located in the display region and multiple drive circuits located in the non-display region.

Abstract: A display substrate and a display device. In the display substrate, at least one of the inter-opening region, the first opening peripheral region and the second opening peripheral region includes a first virtual sub-pixel; the first signal line extends along a first direction and includes a first portion passing through the first opening peripheral region, the inter-opening region and the second opening peripheral region; the first portion passes through the first virtual sub-pixel, and the first virtual sub-pixel includes a first compensation capacitor, a first plate of the first compensation capacitor is in a same layer as the first portion of the first signal line and electrically connected with the first portion of the first signal line, and in a same layer as the second plate of the storage capacitor; the second plate is in a different layer from, insulated from, and overlaps with the first plate.

Abstract: A display substrate and manufacturing method therefor, and a display apparatus. The display substrate comprises driving structure layer comprising multiple light-emitting units and light-emitting structure layer comprising multiple unit rows and at least two dummy rows. A unit row comprises multiple circuit units arranged in a first direction, a dummy row comprises multiple dummy unit arranged in first direction, multiple unit rows and at least two dummy rows are sequentially arranged in a second direction intersecting first direction; at least one dummy row is provided with first connecting line extending in first direction and connected to first initial signal line extending in second direction to form a mesh structure for transmitting first initial signal; and/or at least another dummy row is provided with second connecting line extending in first direction and connected to a second initial signal line extending in second direction to form a mesh structure for transmitting second initial signal.

Abstract: This document describes systems and techniques directed at a machine-learning-based greedy optimization mechanism for reducing radio-frequency (RF) tests in production. In aspects, a process capability index is disclosed, the process capability index used to refine a test-set. The test-set includes tests configured to be performed on an electronic device. The process capability index is configured based on upper specification limits and lower specification limits of the electronic device for each test in the test-set, as well as results for each of the tests in the test-set. The process capability index is further configured based on a new upper specification limit and a new lower specification limit of the electronic device for a new test not in the test-set, as well as results for the new test.