Abstract: The present disclosure provides a performance assessment method and a performance assessment system for prehospital emergency personnel, the performance assessment method of the prehospital emergency personnel comprises: acquiring an employee information of prehospital emergency personnel to be subjected to performance assessment, wherein the employee information comprises a post information; acquiring a performance assessment index set for the post information; acquiring a performance assessment data corresponding to the performance assessment index of the prehospital emergency personnel within a pre-set time period; determining a performance score corresponding to the performance assessment index according to the performance assessment data; obtaining a comprehensive performance score of the prehospital emergency personnel according to a performance score corresponding to each performance assessment index of the prehospital emergency personnel.

Abstract: A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

Abstract: A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

Abstract: A device (100) includes a substrate (101-106) with an upper semiconductor layer, buried semiconductor layer, and a DTI structure (107-108) defining an active device region; a dummy LDMOS device (121) in the active device region which includes a grounded drain (D1) in a drift region (105), a source (S1, S2) in a body region (109) which extends to contact the buried semiconductor layer, a gate electrode (G1-G4) formed so that the source and at least part of the gate electrode are connected with the body implant region, and a buffering semiconductor layer portion (104) adjacent the DTI structure; and one or more active LDMOS devices (122) positioned in the active device region to be separated from the DTI structure by the dummy LDMOS device (121) which reduces an electric field across the sidewall insulator layer (107) in the DTI structure.

Abstract: A device (100) includes a substrate (101-106) with an upper semiconductor layer, buried semiconductor layer, and a DTI structure (107-108) defining an active device region; a dummy LDMOS device (121) in the active device region which includes a grounded drain (D1) in a drift region (105), a source (S1, S2) in a body region (109) which extends to contact the buried semiconductor layer, a gate electrode (G1-G4) formed so that the source and at least part of the gate electrode are connected with the body implant region, and a buffering semiconductor layer portion (104) adjacent the DTI structure; and one or more active LDMOS devices (122) positioned in the active device region to be separated from the DTI structure by the dummy LDMOS device (121) which reduces an electric field across the sidewall insulator layer (107) in the DTI structure.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.

Abstract: A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the trench to remove a first material (38) from the trench. A second material (44) is deposited to plug the opening to seal an air pocket (40) in the trench. The low permittivity region features air pockets with a high volume because the small size of the opening allows the second material to plug the trench without accumulating significantly in the trench.

Abstract: A semiconductor switching device (10) is formed on a semiconductor substrate (12) having a trench (44) formed on one of its surfaces (42). A control electrode (32) activates a wall of the trench to form a conduction channel (36). A first conduction electrode (40) is disposed on the semiconductor substrate to have a first doped region (34) for receiving a current and a second doped region (24) for routing the current to the conduction channel.