Patents by Inventor Yujiro TAKEDA
Yujiro TAKEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230246108Abstract: A transistor includes a bottom gate insulating film, an oxide semiconductor film, a top gate insulating film, a top gate electrode, a first interlayer insulating film, a source electrode, and a drain electrode, wherein the first interlayer insulating film contains carbon atoms, oxygen atoms, hydrogen atoms, and silicon atoms, hydrogen contained in the first interlayer insulating film has a higher concentration than hydrogen contained in the top gate insulating film, and oxygen contained in the first interlayer insulating film has a lower concentration than oxygen contained in the top gate insulating film.Type: ApplicationFiled: April 28, 2020Publication date: August 3, 2023Inventors: IZUMI ISHIDA, YUJIRO TAKEDA, Shinji NAKAJIMA
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Publication number: 20230130571Abstract: An organic EL display device has a frame region provided with a first dam wall and a second dam wall to surround a display region. The first dam wall and the second dam wall include: a first resin wall layer; a first conductive wall layer covering the first resin wall layer; a second resin wall layer over the first resin wall layer through the first conductive wall layer; and a second conductive wall layer covering the second resin wall layer. The second resin wall layer is positioned between: a step portion included in the first conductive wall layer and covering a peripheral end face of the first resin wall layer; and a portion included in the second conductive wall layer and corresponding to the step portion of the first conductive wall layer.Type: ApplicationFiled: April 10, 2020Publication date: April 27, 2023Inventors: SHOGO MURASHIGE, YUJIRO TAKEDA
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Publication number: 20230090537Abstract: A TFT layer is provided that includes a stack of, in sequence, display wires, a protective film, a first flattening film, a metal wire layer and a second flattening film; further, a frame region has a first trench and a second trench respectively provided in the first flattening film and the second flattening film and overlapping the display wires; further, a second electrode is provided to cover the first trench and the second trench; further the protective film includes a first protective film and a third protective film formed of a silicon oxide film, and a second protective film formed of a silicon nitride film.Type: ApplicationFiled: March 2, 2020Publication date: March 23, 2023Inventors: Hirohide MIMURA, SHOGO MURASHIGE, YUJIRO TAKEDA
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Patent number: 11342362Abstract: A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is overlapped with the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.Type: GrantFiled: March 30, 2018Date of Patent: May 24, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Izumi Ishida, Hirohiko Nishiki, Yujiro Takeda
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Patent number: 11145766Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.Type: GrantFiled: June 4, 2018Date of Patent: October 12, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Yujiro Takeda, Hiroshi Matsukizono, Akihiro Oda, Shogo Murashige, Kohhei Tanaka
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Patent number: 11043600Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.Type: GrantFiled: December 15, 2017Date of Patent: June 22, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Shinji Nakajima, Hirohiko Nishiki, Yujiro Takeda, Shogo Murashige
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Publication number: 20210135013Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.Type: ApplicationFiled: December 15, 2017Publication date: May 6, 2021Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Yujiro TAKEDA, Shogo MURASHIGE
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Patent number: 10991725Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.Type: GrantFiled: March 2, 2018Date of Patent: April 27, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Akihiro Oda, Yujiro Takeda, Shogo Murashige, Hiroshi Matsukizono
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Publication number: 20210020662Abstract: A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is superimposed over the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.Type: ApplicationFiled: March 30, 2018Publication date: January 21, 2021Inventors: IZUMI ISHIDA, HIROHIKO NISHIKI, YUJIRO TAKEDA
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Patent number: 10879064Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.Type: GrantFiled: December 15, 2017Date of Patent: December 29, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
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Publication number: 20200243568Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.Type: ApplicationFiled: March 2, 2018Publication date: July 30, 2020Inventors: Akihiro ODA, Yujiro TAKEDA, Shogo MURASHIGE, Hiroshi MATSUKIZONO
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Publication number: 20200194254Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.Type: ApplicationFiled: December 15, 2017Publication date: June 18, 2020Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Hirohide MIMURA, Yuhichi SAITOH, Yujiro TAKEDA, Shogo MURASHIGE, Izumi ISHIDA, Tohru OKABE
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Publication number: 20200152802Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.Type: ApplicationFiled: June 4, 2018Publication date: May 14, 2020Inventors: Yujiro TAKEDA, Hiroshi MATSUKIZONO, Akihiro ODA, Shogo MURASHIGE, Kohhei TANAKA