Abstract: High-speed testing circuitry which, when coupled to one terminal of a multi-terminal electronic device, such as an integrated circuit, can either supply test stimuli signals up to a frequency of 30 MHz, receive output signals produced by the device under test in response to test stimuli signals applied by associated test circuits and compare these signals against computer predicted signals, or provide for parametric testing of the device.

Abstract: An improved testing circuit is provided which includes a pair of comparator circuits each of which is disposed for comparing two minimum threshold amplitudes of responses from a device under test, and a multiplexer circuit coupled to the outputs of the pair of comparator circuits for switching between the outputs of the pair of comparator circuits. The use of a pair of comparator circuits and a multiplexer circuit allows continuous operation of the comparators thereby providing accurate testing at high speeds of operation.The improved testing circuit of this invention also includes a skew adjustment circuit which provides for adjustment of the leading and trailing edges of a test stimuli signal from one testing circuit with respect to the leading and trailing edges of test stimuli signals from other testing circuits incorporated in a circuit testing system.