Patents by Inventor Yuk-Ming Ng
Yuk-Ming Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7721176Abstract: A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.Type: GrantFiled: December 6, 2007Date of Patent: May 18, 2010Assignee: International Business Machines CorporationInventors: Donald Jung, John B. Aylward, Yuk-Ming Ng
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Patent number: 7587543Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.Type: GrantFiled: January 23, 2006Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Daniele Di Genova, Tin-Chee Lo, Yuk-Ming Ng, Jeffrey M. Turner
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Publication number: 20090150732Abstract: A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains. A checkpoint is created of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed. A mainlines test of the integrated circuit is executed. The mainline test includes applying the checkpoint to the integrated circuit, and performing a recovery reset of the stopped domain. It is determined if the mainline test executed correctly and the results of the determining are output.Type: ApplicationFiled: December 6, 2007Publication date: June 11, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donald Jung, John B. Aylward, Yuk-Ming Ng
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Publication number: 20070174530Abstract: A dynamic arbitration controller includes components for reading current state information as well as records of known arbitration states which may cause a deadlock condition, comparing the current state to the records of known arbitration states and resolving deadlock conditions during arbitration. The dynamic arbitration controller may include circuits for storing and retrieving information related to the arbitration. The dynamic arbitration controller may be implemented as a circuit design or as a computer program product stored on machine readable media.Type: ApplicationFiled: January 23, 2006Publication date: July 26, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniele Genova, Tin-Chee Lo, Yuk-Ming Ng, Jeffrey Turner
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Patent number: 7167952Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.Type: GrantFiled: September 17, 2003Date of Patent: January 23, 2007Assignee: International Business Machines CorporationInventors: Krishna M. Desai, Anil S. Keste, Tin-chee Lo, Thomas D. Needham, Yuk-Ming Ng, Jeffrey M. Turner
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Patent number: 7076676Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.Type: GrantFiled: September 24, 2004Date of Patent: July 11, 2006Assignee: International Business Machines CorporationInventors: Tin-chee Lo, Yuk-Ming Ng, Anil S. Keste
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Publication number: 20050060494Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.Type: ApplicationFiled: September 17, 2003Publication date: March 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Krishna Desai, Anil Keste, Tin-Chee Lo, Thomas Needham, Yuk-Ming Ng, Jeffrey Turner
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Publication number: 20050038974Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.Type: ApplicationFiled: September 24, 2004Publication date: February 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tin-chee Lo, Yuk-Ming Ng, Anil Keste
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Patent number: 6836840Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.Type: GrantFiled: July 30, 2001Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Tin-chee Lo, Yuk-Ming Ng, Anil S. Keste
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Publication number: 20030023934Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.Type: ApplicationFiled: July 30, 2001Publication date: January 30, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tin-chee Lo, Yuk-Ming Ng, Anil S. Keste