Abstract: A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Abstract: A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Abstract: A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET.

Abstract: In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X.

Abstract: In one embodiment, a MOSFET model output apparatus is configured to output a MOSFET model for a simulation of a semiconductor circuit. The apparatus includes a shape data input part configured to input shape data of a MOSFET. The apparatus further includes a parameter calculation part configured to calculate a parameter of a parasitic device model to be added to the MOSFET model, using the shape data. The apparatus further includes a MOSFET model output part configured to generate and output the MOSFET model added with the parasitic device model, using the parameter of the parasitic device model. Further, the MOSFET model output part adds different parasitic device models to the MOSFET model in a case where the MOSFET is an N-type MOSFET and in a case where the MOSFET is a P-type MOSFET.

Abstract: In one embodiment, a SPICE model parameter output apparatus is configured to output a SPICE model parameter of a high-frequency or analog MOSFET for a simulation of a semiconductor circuit. The apparatus includes a data input part to input shape data of the MOSFET and measurement data on frequency characteristics of the MOSFET. The apparatus further includes a substrate resistance calculating part configured to calculate a substrate resistance of a one-terminal substrate resistance model regarding the MOSFET, based on the measurement data. The apparatus further includes a SPICE model parameter output part configured to calculate the SPICE model parameter, based on the substrate resistance of the one-terminal substrate resistance model and the shape data, to output the calculated SPICE model parameter.

Abstract: In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X.

Abstract: A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET.