Patents by Inventor Yuka Kuwano

Yuka Kuwano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908659
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuka Kuwano, Takehiko Amaki, Toshikatsu Hida, Shohei Asami
  • Publication number: 20190094927
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
    Type: Application
    Filed: June 18, 2018
    Publication date: March 28, 2019
    Inventors: Yuka KUWANO, Takehiko AMAKI, Toshikatsu HIDA, Shohei ASAMI
  • Publication number: 20170235521
    Abstract: According to one embodiment, a data storage apparatus includes a storage media and a controller. The controller is configured to execute a first process of reading or writing user data from or to the disk storage media which includes a plurality of recording areas, in accordance with a command requested via the host interface, the command including address information that are capable of specifying a recording area; to recognize a first area in which no user data is written, in a case of executing a second process different from the first process on the plurality of recording areas, without designating address information that are capable of specifying a recording area; and to execute the second process on a second area in which user data is written excluding the first area among the plurality of recording areas.
    Type: Application
    Filed: September 8, 2016
    Publication date: August 17, 2017
    Inventors: Yuka Kuwano, Hidekazu Masuyama, Takato Kuji, Kimiyasu Aida, Kenji Inoue
  • Patent number: 9716209
    Abstract: This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region (A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel junction layer is performed in an intermediate phase of a manufacturing process in which the p-type GaN crystal layer is exposed to atmosphere gas with the tunnel junction layer partially removed, before the tunnel junction layer is buried in an n-type GaN crystal layer. In the intermediate phase of the manufacturing process in which the p-type GaN crystal layer is exposed, p-type activation is efficiently performed on the p-type GaN crystal layer, and a p-type GaN crystal layer with low electric resistance can be obtained.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 25, 2017
    Assignee: MELIO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Yuka Kuwano, Motoaki Iwaya, Isamu Akasaki
  • Publication number: 20160365479
    Abstract: This application provides a method of manufacturing an n-p-n nitride-semiconductor light-emitting device which includes a current confinement region(A) using a buried tunnel junction layer and in which a favorable luminous efficacy can be obtained and to provide the n-p-n nitride-semiconductor light-emitting device. The p-type activation of a p-type GaN crystal layer stacked below a tunnel junction layer is performed in an intermediate phase of a manufacturing process in which the p-type GaN crystal layer is exposed to atmosphere gas with the tunnel junction layer partially removed, before the tunnel junction layer is buried in an n-type GaN crystal layer . In the intermediate phase of the manufacturing process in which the p-type GaN crystal layer is exposed, p-type activation is efficiently performed on the p-type GaN crystal layer , and a p-type GaN crystal layer with low electric resistance can be obtained.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 15, 2016
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Yuka KUWANO, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20160170891
    Abstract: According to one embodiment, there is provided a disk apparatus including a disk medium, a nonvolatile memory, and a controller. In the nonvolatile memory, data to be recorded to the disk medium is written. The controller is configured to perform, according to amount of free space of the nonvolatile memory, write process of the data in the nonvolatile memory collectively, or in multiple times with dividing the write process.
    Type: Application
    Filed: March 4, 2015
    Publication date: June 16, 2016
    Inventors: Michio Yamamoto, Isao Fujita, Takumi Kakuya, Masami Tashiro, Yuka Kuwano, Takato Kuji, Katsushi Ohta, Seiji Toda