Abstract: A wiring substrate 11 includes a wiring substrate main body 31 having a semiconductor element mounting area A, a wiring pattern 33 provided on an upper surface 31A of the wiring substrate main body 31 at a portion corresponding to the semiconductor element mounting area A, a solder resist 35 provided on the upper surface 31A of the wiring substrate main body 31 and having an opening portion 43 whose size is substantially equal to the semiconductor element mounting area A when viewed from a top, and a dam 37 provided on the solder resist 35 to block an underfill resin 13 provided in a clearance between the semiconductor element 12 and the wiring substrate main body 31. A distance between an inner wall of the opening portion 43 of the solder resist 35 and an inner wall of the dam 37 is partially varied.

Abstract: A wiring substrate 11 includes a wiring substrate main body 31 having a semiconductor element mounting area A, a wiring pattern 33 provided on an upper surface 31A of the wiring substrate main body 31 at a portion corresponding to the semiconductor element mounting area A, a solder resist 35 provided on the upper surface 31A of the wiring substrate main body 31 and having an opening portion 43 whose size is substantially equal to the semiconductor element mounting area A when viewed from a top, and a dam 37 provided on the solder resist 35 to block an underfill resin 13 provided in a clearance between the semiconductor element 12 and the wiring substrate main body 31. A distance between an inner wall of the opening portion 43 of the solder resist 35 and an inner wall of the dam 37 is partially varied.

Abstract: A semiconductor package 60 in which a region where a land pad 18 is formed is provided on an outer side of a region in which a flip-chip connecting pad 16 is formed, wherein a protecting member 39 is formed to expose the land pad 18 in the region in which the land pad 18 is formed, and the protecting member 39 includes a frame-shaped structure portion 39A disposed to surround the flip-chip connecting pad 16 and a support film portion 39B disposed on an outer side of the frame-shaped structure portion 39A, and a semiconductor device 70 using the semiconductor package 60.

Abstract: A wiring substrate 11 includes a wiring substrate main body 31 having a semiconductor element mounting area A, a wiring pattern 33 provided on an upper surface 31A of the wiring substrate main body 31 at a portion corresponding to the semiconductor element mounting area A, a solder resist 35 provided on the upper surface 31A of the wiring substrate main body 31 and having an opening portion 43 whose size is substantially equal to the semiconductor element mounting area A when viewed from a top, and a dam 37 provided on the solder resist 35 to block an underfill resin 13 provided in a clearance between the semiconductor element 12 and the wiring substrate main body 31. A distance between an inner wall of the opening portion 43 of the solder resist 35 and an inner wall of the dam 37 is partially varied.

Abstract: A semiconductor package 60 in which a region where a land pad 18 is formed is provided on an outer side of a region in which a flip-chip connecting pad 16 is formed, wherein a protecting member 39 is formed to expose the land pad 18 in the region in which the land pad 18 is formed, and the protecting member 39 includes a frame-shaped structure portion 39A disposed to surround the flip-chip connecting pad 16 and a support film portion 39B disposed on an outer side of the frame-shaped structure portion 39A, and a semiconductor device 70 using the semiconductor package 60.

Abstract: Pads to be used for flip chip bonding and wire bonding are pattern-formed on a surface of a substrate. The pads to be used for flip chip bonding are shielded. Plating is applied to each of the pads to be used for wire bonding. Bonding pads for wire bonding is shielded by a masking tape. An adhesive layer is applied to the surface of each of pads to be used for flip chip bonding. Solder powder is provided to adhere to the surface of each of pads to be used for flip chip bonding with the adhesive layer. The masking tape is peeled off from the bonding pads for wire bonding. The solder powder is melted by reflowing so that the solder covers the pads to be used for flip chip bonding.

Abstract: Pads to be used for flip chip bonding and wire bonding are pattern-formed on a surface of a substrate. The pads to be used for flip chip bonding are shielded. Plating is applied to each of the pads to be used for wire bonding. Bonding pads for wire bonding is shielded by a masking tape. An adhesive layer is applied to the surface of each of pads to be used for flip chip bonding. Solder powder is provided to adhere to the surface of each of pads to be used for flip chip bonding with the adhesive layer. The masking tape is peeled off from the bonding pads for wire bonding. The solder powder is melted by reflowing so that the solder covers the pads to be used for flip chip bonding.

Abstract: A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.

Abstract: A multi-layer wiring substrate comprises: a plurality of wiring substrates, each of the substrates comprising a plate or sheet-like insulating layer and a wiring layer formed on only one of surfaces of the insulating layer; the plurality of wiring substrates being laminated in such a manner that the insulating layer and wiring layer are alternately arranged; at least a pair of said wiring layers arranged on respective surfaces of the insulating layer being electrically connected with each other by means of connecting portions formed so as to pass through the insulating layer; and the connecting portion comprises a part of the wiring layer which is extended into a region of an opening formed so as to pass through said insulating layer and a low-melting point metal disposed in the opening and electrically connecting the part of the wiring layer with a wiring substrate formed on an adjacent insulating layer of the laminated structure.