Patents by Inventor Yuka Terai

Yuka Terai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130242149
    Abstract: A solid-state imaging device includes: a semiconductor substrate including a matrix of photoelectric converters disposed therein; a transparent insulating layer disposed on the semiconductor substrate and including wiring lines embedded therein; a color filter layer disposed on the transparent insulating layer and including a color filter for each of a plurality of colors of the respective photoelectric converters; and a plurality of microlenses disposed on the color filter layer, one for each color filter. In a plan view, the color filter of at least one color is smaller in area size than the corresponding microlens. In the color filter layer, the color filter of the at least one color is surrounded by a low-refractive-index material having a lower refractive index than a refractive index of the color filter.
    Type: Application
    Filed: May 6, 2013
    Publication date: September 19, 2013
    Applicant: Panasonic Corporation
    Inventors: YUKA TERAI, ATSUO NAKAGAWA
  • Patent number: 7171640
    Abstract: A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit storing design layout information including the design layout configuration of the semiconductor integrated circuit, and a predicted final layout memory storing a predicted final layout configuration predicted by the central processing unit by adding an optical proximity effect to the design layout configuration. The system further has a netlister which describes a procedure for causing the central processing unit to produce a plurality of net lists in which different physical values are registered for a common element in the predicted final layout configuration, a netlist memory unit the plurality of net lists, and a circuit simulator which describes a procedure for causing the central processing unit to perform operation verification of the semiconductor integrated circuit by using an arbitrary one of the plurality of net lists.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuka Terai, Kyoji Yamashita
  • Publication number: 20060010407
    Abstract: A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit which stores therein design layout information including the design layout configuration of the semiconductor integrated circuit in which a plurality of semiconductor elements are integrated, and a predicted final layout memory unit which stores therein a predicted final layout configuration that has been predicted by the central processing unit by adding an optical proximity effect to the design layout configuration.
    Type: Application
    Filed: May 27, 2005
    Publication date: January 12, 2006
    Inventors: Yuka Terai, Kyoji Yamashita
  • Patent number: 6372928
    Abstract: A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: wherein X1 and X2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y1, Y2 and Y3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R1 and R2 is any of SiF3, SiH3, CF3 and CH3 for example.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: April 16, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akemi Kawaguchi, Yuka Terai, Kousaku Yano
  • Patent number: 5863338
    Abstract: A forming apparatus of a thin film, includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate, and a feeding device, which is provided in the processing chamber, for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film, includes steps of forming a thin film on a surface of a supplied substrate in a processing chamber, and feeding material for forming an organic molecular layer including silicon or germanium on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: January 26, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuichiro Yamada, Naoki Suzuki, Ryuzo Houchin, Noboru Nomura, Kousaku Yano, Yuka Terai
  • Patent number: 5773639
    Abstract: A layer forming material is a compound which has a structure of six-membered ring coordinated to Cu and containing Si, and of which general formula is represented by the following chemical formula: ##STR1## wherein X.sub.1 and X.sub.2 are elements of the VI group of the same or different types which are coordinate-bonded to Cu, and of which examples include O, S, Se, Te and the like, at least one of Y.sub.1, Y.sub.2 and Y.sub.3 is Si, L is a group which has a double or triple bond and which is able to supply electrons to Cu, and each of R.sub.1 and R.sub.2 is any of SiF.sub.3, SiH.sub.3, CF.sub.3 and CH.sub.3 for example.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: June 30, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akemi Kawaguchi, Yuka Terai, Kousaku Yano
  • Patent number: 5693557
    Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: December 2, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Hirao, Hisashi Ogawa, Yuka Terai, Mitsuru Sekiguchi, Masanori Fukumoto, Isao Miyanaga
  • Patent number: 5661068
    Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 26, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Hirao, Hisashi Ogawa, Yuka Terai, Mitsuru Sekiguchi, Masanori Fukumoto, Isao Miyanaga
  • Patent number: 5633211
    Abstract: The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: May 27, 1997
    Assignee: Matsushita Electric Industrial Co., Ld.
    Inventors: Shinichi Imai, Yuka Terai, Masanori Fukumoto, Kousaku Yano, Hiroyuki Umimoto, Shinji Odanaka, Yasuo Mizuno
  • Patent number: 5576247
    Abstract: A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: November 19, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kousaku Yano, Masayuki Endo, Yuka Terai, Noboru Nomura, Tomoyasu Murakami, Tetsuya Ueda, Satoshi Ueda
  • Patent number: 5501739
    Abstract: A forming apparatus of a thin film includes a processing chamber where a predetermined process is carried out on a surface of a supplied substrate. A feeding device is provided in the processing chamber for feeding material to form an organic molecular layer including silicon or germanium on the surface of the substrate. A forming method of a thin film includes the steps of forming the thin film on the surface of the supplied substrate in the processing chamber, and feeding material for forming the organic molecular layer, including silicon or germanium, on the formed thin film on the surface of the substrate through a feeding device in the processing chamber, and then forming the organic molecular layer on the surface of the substrate.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: March 26, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuichiro Yamada, Naoki Suzuki, Ryuzo Houchin, Noboru Nomura, Kousaku Yano, Yuka Terai
  • Patent number: 5474949
    Abstract: A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.
    Type: Grant
    Filed: January 26, 1993
    Date of Patent: December 12, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shuji Hirao, Hisashi Ogawa, Yuka Terai, Mitsuru Sekiguchi, Masanori Fukumoto, Isao Miyanaga
  • Patent number: 5314848
    Abstract: Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.
    Type: Grant
    Filed: September 24, 1991
    Date of Patent: May 24, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takatoshi Yasui, Chiaki Kudo, Ichiro Nakao, Toyokazu Fujii, Yuka Terai, Shinichi Imai, Hiroshi Yamamoto, Yasushi Naito