Patents by Inventor Yukari Imai
Yukari Imai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8344511Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.Type: GrantFiled: March 7, 2012Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Kazuhito Ichinose, Yukari Imai
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Publication number: 20120161244Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Applicant: Renesas Electronics CorporationInventors: Kazuhito ICHINOSE, Yukari Imai
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Patent number: 8158473Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.Type: GrantFiled: February 2, 2010Date of Patent: April 17, 2012Assignee: Renesas Electronics CorporationInventors: Kazuhito Ichinose, Yukari Imai
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Publication number: 20100200928Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.Type: ApplicationFiled: February 2, 2010Publication date: August 12, 2010Inventors: Kazuhito ICHINOSE, Yukari Imai
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Patent number: 6745618Abstract: A scanning probe microscope includes a laser diode (1a) as a light source for emitting light lower in energy level than band gap of semiconductor as a sample. Laser light (2) emitted therefrom should be of wavelength larger in value than a wavelength &lgr; calculated as follows: &lgr;=h·c/Eg where h is Planck's constant, c represents speed of light and Eg represents band gap. When the semiconductor as a sample is silicon, the band gap thereof is 1.12 eV, thus calculating the wavelength &lgr; at 1.107 &mgr;m. The laser diode (1a) should be such that the laser light (2) emitted therefrom is of wavelength larger in value than &lgr;. It is therefore allowed to avoid emission of light higher in energy level than the band gap of silicon as a sample and eventually, avoid generation of photoelectric current in the sample.Type: GrantFiled: July 12, 2002Date of Patent: June 8, 2004Assignee: Renesas Technology Corp.Inventors: Yukari Imai, Mari Tsugami, Hitoshi Maeda, Tohru Koyama
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Publication number: 20040103353Abstract: A failure analysis device and a failure analysis method which enable easily a specification of a position of a failure point which is obtained from a back side upon a wiring pattern image which is obtained from a front side is provided.Type: ApplicationFiled: July 17, 2003Publication date: May 27, 2004Applicant: Renesas Technology Corp.Inventors: Tohru Koyama, Yukari Imai
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Publication number: 20030115939Abstract: A scanning probe microscope includes a laser diode (1a) as a light source for emitting light lower in energy level than band gap of semiconductor as a sample.Type: ApplicationFiled: July 12, 2002Publication date: June 26, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yukari Imai, Mari Tsugami, Hitoshi Maeda, Tohru Koyama
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Patent number: 6545470Abstract: It is an object to obtain a scanning probe microscope capable of effectively suppressing a reduction in precision in a measurement. A conductive probe (2C) has such a pyramid structure as to be expanded from a tip portion to a bottom surface (a surface on which a cantilever (1) is to be formed) and a semiconductor integrated circuit (12) is formed in a side surface of the conductive probe (2C). An amplifying circuit (12a) to be the semiconductor integrated circuit (12) amplifies an electrical characteristic signal given from the conductive probe (2C) to send the electrical characteristic signal to a signal processor (10) through a conductive cantilever (1C) and a signal cable (9).Type: GrantFiled: April 1, 2002Date of Patent: April 8, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukari Imai, Hitoshi Maeda, Mari Tsugami, Yoji Mashiko
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Publication number: 20030057988Abstract: A semiconductor device inspecting method is provided which can detect electric faults in an in-line inspection. The positive electrode of a variable DC power supply (2) is connected to the back or a peripheral portion of a semiconductor substrate (4) and the negative electrode of the variable DC power supply (2) is connected to a conductive cantilever (3). A scan is performed with a given forward bias voltage (e.g. 1.0 V) applied between the cantilever (3) and the semiconductor substrate (4) and with the cantilever (3) in contact with a target contact plug (9). The current flowing through the cantilever (3) is then monitored with an ammeter (1) to obtain a current characteristic of each contact plug, making it possible to detect conduction faults which cannot be detected by simply observing the configuration.Type: ApplicationFiled: June 4, 2002Publication date: March 27, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hitoshi Maeda, Fumihito Ohta, Yukari Imai, Toshikazu Tsutsui
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Publication number: 20030025498Abstract: It is an object to obtain a scanning probe microscope capable of effectively suppressing a reduction in precision in a measurement. A conductive probe (2C) has such a pyramid structure as to be expanded from a tip portion to a bottom surface (a surface on which a cantilever (1) is to be formed) and a semiconductor integrated circuit (12) is formed in a side surface of the conductive probe (2C). An amplifying circuit (12a) to be the semiconductor integrated circuit (12) amplifies an electrical characteristic signal given from the conductive probe (2C) to send the electrical characteristic signal to a signal processor (10) through a conductive cantilever (1C) and a signal cable (9) (FIG. 1).Type: ApplicationFiled: April 1, 2002Publication date: February 6, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yukari Imai, Hitoshi Maeda, Mari Tsugami, Yoji Mashiko
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Patent number: 5850149Abstract: A part of a gate insulation film between a semiconductor substrate and an exposed gate electrode of a semiconductor device is partially and stepwise etched away. A voltage is applied between the semiconductor substrate and the gate electrode in a chemical wet etching system at each step. An anode oxide film is formed on the surface of the gate electrode in a step, when a defect is included in a gate oxide film. The gate electrode is etched away in another step, when a defect is not included in the gate oxide film. A position of a defect in the gate insulation film is detected from the difference in the area of the gate insulation film when an anode oxide film is formed on the gate electrode, and when the gate electrode is etched away.Type: GrantFiled: November 25, 1996Date of Patent: December 15, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiharu Katayama, Naoko Ohtani, Yukari Imai
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Patent number: 5677204Abstract: A semiconductor device (100) including a silicon substrate (1), a gate oxide film (2) formed on the silicon substrate (1) and having a defect (3) and a dielectric breakdown voltage failure portion (4), and a polysilicon film (5) formed on the gate oxide film (2) is immersed in a chemical etchant (7) in a wet etching apparatus (9). With the silicon substrate (1) serving as an anode, a DC voltage source (6) of the wet etching apparatus (9) applies voltage to the silicon substrate (1) to perform anode oxidation. Passivation layers (10) are formed on parts of the surface of the polysilicon film (5) which overlies the defect (3) and dielectric breakdown voltage failure portion (4) but are not formed on the surface of the polysilicon film (5) in regions insulated by the gate oxide film (2). The polysilicon film (5) in the regions on which the passivation layers (10) are not formed is removed by the chemical etchant (7).Type: GrantFiled: April 10, 1996Date of Patent: October 14, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukari Imai, Toshiharu Katayama, Naoko Otani
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Patent number: 5633184Abstract: A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.Type: GrantFiled: February 9, 1995Date of Patent: May 27, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuhiko Tamura, Yukari Imai, Naoko Otani
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Patent number: 5434813Abstract: A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.Type: GrantFiled: August 31, 1993Date of Patent: July 18, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuhiko Tamura, Yukari Imai, Naoko Otani