Abstract: An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priority information provided from processors, specifies a processor that is presenting priority information with the highest priority, i.e. a processor with the highest priority level, and outputs the result of the check (CHK) to the round robin block (22). The round robin block (22), holding the results of the previous arbitration process, generates and outputs a processor selecting signal (SE) on the basis of the priority check result (CHK) and a round robin order generated from the previous results.

Abstract: An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priority information provided from processors, specifies a processor that is presenting priority information with the highest priority, i.e. a processor with the highest priority level, and outputs the result of the check (CHK) to the round robin block (22). The round robin block (22), holding the results of the previous arbitration process, generates and outputs a processor selecting signal (SE) on the basis of the priority check result (CHK) and a round robin order generated from the previous results.

Abstract: Provided is a data processor capable of preferentially starting an interrupt processing when an interrupt request occurs during burst transfer to cache memory. When an interrupt request (IR) is detected during burst transfer to an instruction cache (3), the instruction cache (3) suspends the burst transfer and creates break information (35). Upon return to the original program at the termination of the interrupt processing, the instruction cache (3) restarts the burst transfer from the suspended point by referring to a restart address described in an address description part (35a) of the break information (35).

Abstract: A microcomputer comprises a processor, a memory and a buffer including a selector for changing a bus width, wherein a processor bus has a smaller width than that of a memory bus. The microcomputer further comprises a bus interface unit which has a selector for changing the bus width, and is used for inputting/outputting signals from/to the outside, and an external bus for connecting the bus interface unit and the outside, wherein the bus interface unit is connected to the memory via the memory bus, and the external bus has a smaller width than that of the memory bus. Still further the memory includes a plurality of memory regions, and the processor is disposed in a space of the memory regions.

Abstract: In a microprocesssor (101), a selector (7) is connected to a bus ID <0:127> through a write buffer (5) and a DRAM (27), a cache (28) and an IQ (8) are also connected to the bus ID <0:127>. The bus ID <0:127> and the microprocessor (101) are connected to the external memory (4) and the external bus master (41) with a data bus D <0:15> through a BIU (3). The microprocessor (101) is also connected to the external memory (4) and the external bus master (41) with an address bus (58) and control bus (57). The BIU (3) controls an access to a memory integrated in the microprocessor (101) and a memory externally connected thereto. With this configuration, the DRAM and the cache can be integrated together in the microprocessor which is externally connected to the bus master.

Abstract: A priority encoder which, when an instruction for transferring a plurality of register contents is executed, encodes two or more register addresses to which the contents are to be transferred from a register list, and a data processor capable of transferring two or more register contents simultaneously by comprising the same,

Abstract: A data processor which performs in parallel a comparison process of n (which is an integer 2 or more)--sets first size data a elements by logical add operation between data elements in executing a first instruction for processing simultaneously number of n first size data elements, and performs a comparison process of one-set second size data elements by logical product operation of the compared results of whole data elements in executing a second instruction for processing individually second size data elements whose size is n times of said first size.

Abstract: A data processing circuit being provided with a select and output circuit 5 selectively outputting an operation result of an arithmetic logic unit (ALU)4 to a D bus 8, a temporary latch 2 holding a data part of a register 11 into which the operation result is written, and a select and output circuit 3 selectively outputting the data held in the temporary latch 2 to the D bus 8, wherein the select and output circuit 5 for the ALU 4 outputs only bits corresponding to a designated writing size to the D bus 8, the select and output circuit 3 for the temporary latch 2 outputs other than bits corresponding to the designated writing size to the D bus 8, and the register 11 inputs and stores data from the D bus 8, thereby leading to be capable of reducing the area of the register file 1.

Abstract: A register address specifying circuit capable of, besides accessing a register whose address is specified address, accessing also a register whose register address which is one address different from the specified register address, when executing the instruction for transferring a plurality of register contents, and a data processor which is able to access and transfer two register contents at the same time by comprising the same.