Abstract: A vehicle having a rear fender disposed above a rear wheel and formed of a plate member having an upward projecting shape, includes a cover member which covers a portion of a lower open part of the rear fender on a lateral side of the rear wheel. The rear fender and the cover member are provided as separate bodies to keep the moldability of the rear fender favorable. The mud-guard performance can be enhanced by covering part of the lower open part of the rear fender by the cover member. Such configuration provides a vehicle in which the mud-guard performance can be enhanced while keeping the moldability of a rear fender favorable.

Abstract: A vehicle having a rear fender disposed above a rear wheel and formed of a plate member having an upward projecting shape, includes a cover member which covers a portion of a lower open part of the rear fender on a lateral side of the rear wheel. The rear fender and the cover member are provided as separate bodies to keep the moldability of the rear fender favorable. The mud-guard performance can be enhanced by covering part of the lower open part of the rear fender by the cover member. Such configuration provides a vehicle in which the mud-guard performance can be enhanced while keeping the moldability of a rear fender favorable.

Abstract: This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Abstract: A high-speed encoding apparatus retrieves the bit position of either one of the lowest order bit or the highest order bit having a first logical value. Such retrieving starts from a selected bit-position. The selected bit-position is defined by an input offset value Iofs4:Iofs0. The retrieved bit-position is the output of the encoder Oofs4:Oofs0. A zero detection circuit receives an n-bit data word, segments the n-bits into groups of predetermined length and for each group generates a zero detection when all bits in the group are zero. The zero detection circuit also masks the zero detections according to the high order bit states of the input offset value. A first encoder then generates the high order bits of the apparatus output offset in response to the masked and unmasked zero detections. A second encoder masks one or more of the groups according to the bit states of the input offset value, then generates encoded bit sets for each group.

Abstract: This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.