Patents by Inventor Yuki Ebihara

Yuki Ebihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11805638
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: October 31, 2023
    Inventors: Seiji Narui, Yuki Ebihara
  • Publication number: 20210225848
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 22, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Yuki Ebihara
  • Patent number: 10964702
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Seiji Narui, Yuki Ebihara
  • Patent number: 10922262
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10854310
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Publication number: 20200233828
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10664432
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Publication number: 20200126993
    Abstract: Apparatuses including a first-in first-out circuit are described. An example apparatus includes: a first-in first-out circuit including a first latch, a second latch and a logic circuit coupled in series. The first latch receives first data and latches the first data responsive to a first input pointer signal. The second latch receives the latched first data from the first latch and latches the received first data responsive to a second input pointer signal that has a different phase from the first input pointer signal and thus provides a second data. The logic circuit receives the second data and an output pointer signal and further provides an output data responsive to the output pointer signal.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Seiji Narui, Yuki Ebihara
  • Patent number: 10614024
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Publication number: 20190361835
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10468114
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Publication number: 20190295679
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Publication number: 20180301202
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Application
    Filed: June 20, 2018
    Publication date: October 18, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Patent number: 10008287
    Abstract: Apparatuses and methods for an interface chip are described. An example apparatus includes a first chip. The first chip includes, on a single semiconductor substrate, first terminals, circuit groups, and terminal groups corresponding to the circuit groups, each of the circuit groups including circuit blocks. A control circuit in the first chip selects one of the circuit groups and electrically couples the first terminals to the circuit blocks of the selected circuit group. Second terminals are included in each of the terminal groups. A number of all of the second terminals in each of the terminal groups is smaller than a number of all of the circuit blocks in the corresponding circuit group. The first chip further includes, for example, a remapping circuit.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
  • Publication number: 20180025789
    Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.
    Type: Application
    Filed: July 22, 2016
    Publication date: January 25, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara