Patents by Inventor Yuki Haraguchi
Yuki Haraguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072124Abstract: Provided is a semiconductor device and a method of manufacturing a semiconductor device in which deterioration of energy loss is suppressed. The semiconductor device includes: a drift layer of a first conductivity type provided between a first main surface and a second main surface of a semiconductor substrate; and a field stop layer of the first conductivity type having an impurity concentration higher than that of the drift layer and provided between the drift layer and the second main surface. A net carrier concentration profile at room temperature of the field stop layer have at least one peak from the second main surface toward the first main surface. A hydrogen atom concentration profile of the field stop layer have at least two peaks from the second main surface toward the first main surface. The hydrogen atom concentration profile has more peaks than the net carrier concentration profile.Type: ApplicationFiled: June 13, 2023Publication date: February 29, 2024Applicant: Mitsubishi Electric CorporationInventors: Yusuke MIYATA, Kenji SUZUKI, Yuki HARAGUCHI, Haruhiko MINAMITAKE, Taiki HOSHI, Hidenori KOKETSU
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Patent number: 11881504Abstract: A semiconductor device according to the present disclosure includes: a first conductivity-type silicon substrate including a cell part and a termination part surrounding the cell part in plan view; a first conductivity-type emitter layer provided on a front surface of the silicon substrate in the cell part; a second conductivity-type collector layer provided on a back surface of the silicon substrate in the cell part; a first conductivity-type drift layer provided between the emitter layer and the collector layer; a trench gate provided to reach the drift layer from a front surface of the emitter layer; and a second conductivity-type well layer provided on the front surface of the silicon substrate in the termination part. Vacancies included in a crystal defect in the cell part are less than vacancies included in a crystal defect in the termination part.Type: GrantFiled: September 13, 2021Date of Patent: January 23, 2024Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Yuki Haraguchi, Haruhiko Minamitake, Taiki Hoshi, Takuya Yoshida, Hidenori Koketsu, Yusuke Miyata, Akira Kiyoi
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Publication number: 20230420524Abstract: A first buffer layer includes: a first region containing protons and in contact with a drift layer; a second region between the first region and a first principal surface containing protons, and in contact with the first region; and a third region between the second region of the first buffer layer and the first principal surface. An impurity concentration profile of the first buffer layer includes: a maximum value in the second region; a kink at a boundary point between the first region and the second region, relaxing or stopping a decrease from the maximum value; a value at the boundary point higher than or equal to 80% of the maximum value; and a distribution of the third region longer than or equal to 5 ?m and having an impurity concentration lower than the value at the boundary point and lower than or equal to 5.0×1014/cm3.Type: ApplicationFiled: April 26, 2023Publication date: December 28, 2023Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Yuki HARAGUCHI, Haruhiko MINAMITAKE, Taiki HOSHI, Hidenori KOKETSU, Yusuke MIYATA
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Publication number: 20230387218Abstract: A semiconductor device includes a drift region that is of first conductive type and formed in a semiconductor substrate; a hydrogen buffer region that is of first conductive type, positioned on the back surface side of the drift region, contains hydrogen as impurities, and has impurity concentration higher than impurity concentration of the drift region; a flat region that is of first conductive type, positioned on the back surface side of the hydrogen buffer region, and has impurity concentration higher than impurity concentration of the drift region; and a carrier injection layer that is of first or second conductive type, positioned on the back surface side of the flat region, and has impurity concentration higher than impurity concentrations of the hydrogen buffer region and the flat region. The hydrogen buffer region and the flat region each have a constant oxygen concentration of 1E16 atoms/cm3 to 6E17 atoms/cm3 inclusive.Type: ApplicationFiled: February 1, 2023Publication date: November 30, 2023Applicant: Mitsubishi Electric CorporationInventors: Taiki HOSHI, Kenji SUZUKI, Yuki HARAGUCHI, Haruhiko MINAMITAKE, Hidenori KOKETSU, Yusuke MIYATA, Akira KIYOI
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Patent number: 11824084Abstract: An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n? type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films.Type: GrantFiled: August 16, 2021Date of Patent: November 21, 2023Assignee: Mitsubishi Electric CorporationInventors: Yuki Haraguchi, Fumihito Masuoka, Ze Chen
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Publication number: 20220181435Abstract: A semiconductor device according to the present disclosure includes: a first conductivity-type silicon substrate including a cell part and a termination part surrounding the cell part in plan view; a first conductivity-type emitter layer provided on a front surface of the silicon substrate in the cell part; a second conductivity-type collector layer provided on a back surface of the silicon substrate in the cell part; a first conductivity-type drift layer provided between the emitter layer and the collector layer; a trench gate provided to reach the drift layer from a front surface of the emitter layer; and a second conductivity-type well layer provided on the front surface of the silicon substrate in the termination part. Vacancies included in a crystal defect in the cell part are less than vacancies included in a crystal defect in the termination part.Type: ApplicationFiled: September 13, 2021Publication date: June 9, 2022Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Yuki HARAGUCHI, Haruhiko MINAMITAKE, Taiki HOSHI, Takuya YOSHIDA, Hidenori KOKETSU, Yusuke MIYATA, Akira KIYOI
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Publication number: 20220173094Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a diode trench gate, and an electrode layer. The first semiconductor layer is provided as a surface layer on the upper surface side of the semiconductor substrate. The second semiconductor layer is provided below the first semiconductor layer. The diode trench gate includes a diode trench insulation film formed along, out of the inner wall of the trench, a lower side wall and a bottom that are located below an upper side wall located on the upper end side of the trench. The diode trench gate includes a diode trench electrode provided inside the trench. The electrode layer covers the upper side wall of the trench. The first semiconductor layer is in contact with the electrode layer on the upper side wall of the trench.Type: ApplicationFiled: August 23, 2021Publication date: June 2, 2022Applicant: Mitsubishi Electric CorporationInventors: Takuya YOSHIDA, Kenji SUZUKI, Yuki HARAGUCHI, Hidenori KOKETSU
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Publication number: 20220130951Abstract: An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n? type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films and.Type: ApplicationFiled: August 16, 2021Publication date: April 28, 2022Applicant: Mitsubishi Electric CorporationInventors: Yuki HARAGUCHI, Fumihito MASUOKA, Ze CHEN
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Patent number: 11004932Abstract: The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.Type: GrantFiled: April 8, 2020Date of Patent: May 11, 2021Assignee: Mitsubishi Electric CorporationInventors: Ze Chen, Fumihito Masuoka, Yuki Haraguchi
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Publication number: 20200388673Abstract: The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.Type: ApplicationFiled: April 8, 2020Publication date: December 10, 2020Applicant: Mitsubishi Electric CorporationInventors: Ze CHEN, Fumihito MASUOKA, Yuki HARAGUCHI
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Patent number: 10658523Abstract: The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p+-type anode layer disposed to include a position right under a portion where the wire is connected; and a p?-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p+-type anode layer is higher than an impurity concentration of the p?-type anode layer.Type: GrantFiled: October 17, 2018Date of Patent: May 19, 2020Assignee: Mitsubishi Electric CorporationInventors: Shigeto Honda, Fumihito Masuoka, Yuki Haraguchi
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Patent number: 10474292Abstract: An information reception device is provided with: operation surface which is adjusted to produce a characteristic index vibration by an object contact; a storage device stores candidate information (candidate information is related with the index vibration) which serves as a candidate of input information; a microphone which acquires observation information according to observation of the actual vibration arising in the surrounding environment; and a CPU. The CPU (selecting part) judges whether or not the index vibration exists in the observation information acquired. When the CPU judges that the index vibration exists, the CPU selects the candidate information which is related with the index vibration as the input information.Type: GrantFiled: September 15, 2017Date of Patent: November 12, 2019Assignees: MEGACHIPS CORPORATION, NITTO DENKO CORPORATIONInventors: Motoyasu Tanaka, Takashi Matsutani, Masayasu Yamamoto, Yuki Haraguchi, Hideo Sugawara, Ikuo Kawamoto, Motoki Haishi, Nobuyuki Kozonoi
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Publication number: 20190157466Abstract: The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p+-type anode layer disposed to include a position right under a portion where the wire is connected; and a p?-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p+-type anode layer is higher than an impurity concentration of the p?-type anode layer.Type: ApplicationFiled: October 17, 2018Publication date: May 23, 2019Applicant: Mitsubishi Electric CorporationInventors: Shigeto HONDA, Fumihito MASUOKA, Yuki HARAGUCHI
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Patent number: 10284831Abstract: Provided is a projection system that sets an arbitrary three-dimensional shape as a projection target and properly corrects geometric distortion of a projected image even when a user's viewpoint is not fixed. A projection unit of the projector apparatus projects a test image for first adjustment. A three-dimensional shape measurement unit measures the three-dimensional shape of the projection target. An image capturing apparatus captures the test image for first adjustment projected by the projection unit to obtain a captured image for first adjustment.Type: GrantFiled: September 18, 2017Date of Patent: May 7, 2019Assignees: MEGACHIPS CORPORATION, NINTENDO CO., LTD.Inventors: Motoyasu Tanaka, Yuki Haraguchi, Fumiya Shingu, Eizi Kawai, Kazuhiro Hosoi
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Patent number: 10223583Abstract: In an object detection apparatus 1, a window definer 11 defines a window relative to the location of a pixel in an input image 20. A classification value calculator 13 calculates a classification value indicative of the likelihood that a detection target is present in the window image contained in the window based on the feature data of the detection target. A classification image generator 14 arranges the classification value calculated from the window image according to the pixel location to generate a classification image. An integrator 15 integrates the classification image and a past classification image 42 generated from a past input image input prior to the input image 20 to generate an integrated image 45. A determiner 16 determines whether the detection target is present in the input image 20 based on the integrated image 45.Type: GrantFiled: November 21, 2016Date of Patent: March 5, 2019Assignee: MegaChips CorporationInventors: Yuki Haraguchi, Hiromu Hasegawa
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Patent number: 9977967Abstract: The object detection device 1 detects an object being recognized (such as a pedestrian) in a frame image 42, and identifies an area 42a where a detected object which is detected in the frame image 42 is present. A frame image 43 is input after the frame image 42. The object detection device 1 detects the object being recognized in the frame image 43, and identifies an area 43a where a detected object which is detected in the frame image 43 is present. When a distance from center coordinates 42b of the area 42a to center coordinates 43b of the area 43a is smaller than a reference distance, the object detection device 1 determines that the detected object which is detected in the frame image 43 is identical to the detected object which is detected in the frame image 42.Type: GrantFiled: April 13, 2017Date of Patent: May 22, 2018Assignee: MegaChips CorporationInventors: Taizo Umezaki, Yuki Haraguchi, Hiromu Hasegawa
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Patent number: 9964839Abstract: Even when a high-performance imaging apparatus is not used, luminance unevenness and color unevenness of an image (video) projected on a projection plane by the projection type projector apparatus are appropriately reduced. Using a coefficient Br (0?Br?1) set by a coefficient setting unit, the projection system obtains, based on the gamma characteristic of the entire system of the projection system, a target image for reducing the number of pixels saturated when the image is projected. Then, the projection system performs correction processing using the obtained target image based on the gamma characteristic of the entire system of the projection system and a white value. This reduces the number of saturated pixels of the projected image in the projection system.Type: GrantFiled: September 29, 2017Date of Patent: May 8, 2018Assignees: MegaChips Corporation, The University of Electro-CommunicationsInventors: Naoki Hashimoto, Chiharu Kohari, Yuki Haraguchi, Fumiya Shingu, Motoyasu Tanaka
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Patent number: 9928580Abstract: Provided is a projection system that easily and appropriately reduces the geometric distortion of the image projected on the projection plane. The projection circuitry 3 of the projection system 1000 projects a test image onto the projection plane. The three-dimensional shape measurement circuitry 4 measures the three-dimensional shape of the projection plane. The controller 200 generates a control signal. Based on the measured three-dimensional shape data, the projection image adjustment circuitry 1 performs correction processing and rotation processing on a test, in accordance with the control signal, such that the geometrical image distortion is reduced as viewed from the user's viewpoint.Type: GrantFiled: September 28, 2017Date of Patent: March 27, 2018Assignees: MegaChips Corporation, Nintendo Co., Ltd.Inventors: Motoyasu Tanaka, Yuki Haraguchi, Fumiya Shingu, Eizi Kawai, Kazuhiro Hosoi
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Publication number: 20180024423Abstract: Even when a high-performance imaging apparatus is not used, luminance unevenness and color unevenness of an image (video) projected on a projection plane by the projection type projector apparatus are appropriately reduced. Using a coefficient Br (0?Br?1) set by a coefficient setting unit, the projection system obtains, based on the gamma characteristic of the entire system of the projection system, a target image for reducing the number of pixels saturated when the image is projected. Then, the projection system performs correction processing using the obtained target image based on the gamma characteristic of the entire system of the projection system and a white value. This reduces the number of saturated pixels of the projected image in the projection system.Type: ApplicationFiled: September 29, 2017Publication date: January 25, 2018Applicants: MegaChips Corporation, The University of Electro-CommunicationsInventors: Naoki HASHIMOTO, Chiharu KOHARI, Yuki HARAGUCHI, Fumiya SHINGU, Motoyasu TANAKA
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Publication number: 20180018761Abstract: Provided is a projection system that easily and appropriately reduces the geometric distortion of the image projected on the projection plane. The projection circuitry 3 of the projection system 1000 projects a test image onto the projection plane. The three-dimensional shape measurement circuitry 4 measures the three-dimensional shape of the projection plane. The controller 200 generates a control signal. Based on the measured three-dimensional shape data, the projection image adjustment circuitry 1 performs correction processing and rotation processing on a test, in accordance with the control signal, such that the geometrical image distortion is reduced as viewed from the user's viewpoint.Type: ApplicationFiled: September 28, 2017Publication date: January 18, 2018Applicants: MegaChips Corporation, Nintendo Co., Ltd.Inventors: Motoyasu TANAKA, Yuki HARAGUCHI, Fumiya SHINGU, Eizi KAWAI, Kazuhiro HOSOI