Patents by Inventor Yuki Hashimoto

Yuki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8834233
    Abstract: A method for producing an implant whose surface is roughened by the sandblast method using shot material containing fluoroapatite. Fluoroapatite, compared to hydroxyapatite, has poor biocompatibility, but is superior in hardness. It also has a property of being dissolved in acid. As a result, by the sandblast method using shot material containing fluoroapatite, the surface roughening is performed quite effectively, and shot materials remained on the surface can easily be removed by acid.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: September 16, 2014
    Assignee: Yamahachi Dental Mfg., Co.
    Inventors: Hideki Aoki, Masashi Toyama, Hiroto Fujimaki, Yuki Hashimoto
  • Patent number: 8018673
    Abstract: A disk drive. The disk drive includes a plurality of head-sliders, an actuator, a plurality of clearance adjustment sections, and a controller. Each head-slider includes a slider and a magnetic-recording head on the slider for accessing a disk for storing data. The plurality of head-sliders is secured to the actuator that is configured to move the plurality of head-sliders concurrently. Each clearance adjustment section corresponds to each head-slider of the plurality of head-sliders and adjusts a clearance of the corresponding head-slider. In addition, the controller is configured to position the actuator by servo control with a first head-slider selected from the plurality of head-sliders, to change a clearance of a second head-slider different from the first head-slider by controlling a clearance adjustment section of the second head-slider to bring the second head-slider into contact with a disk, and to detect the contact to measure the clearance of the second head-slider.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: September 13, 2011
    Assignee: Hitachi Global Storage Technologies, Netherlands B.V.
    Inventors: Manabu Saikawa, Atsushi Takeichi, Yuki Hashimoto, Kenji Kuroki, Mitsuhiro Shoda
  • Publication number: 20100243429
    Abstract: A method for producing an implant whose surface is roughened by the sandblast method using shot material containing fluoroapatite. Fluoroapatite, compared to hydroxyapatite, has poor biocompatibility, but is superior in hardness. It also has a property of being dissolved in acid. As a result, by the sandblast method using shot material containing fluoroapatite, the surface roughening is performed quite effectively, and shot materials remained on the surface can easily be removed by acid.
    Type: Application
    Filed: December 9, 2008
    Publication date: September 30, 2010
    Applicant: YAMAHACHI DENTAL MFG., CO.
    Inventors: Hideki Aoki, Masashi Toyama, Hiroto Fujimaki, Yuki Hashimoto
  • Publication number: 20100204320
    Abstract: A method for preventing or treating xerosis by applying a prostaglandin D receptor selective agonist to a mammal.
    Type: Application
    Filed: April 19, 2010
    Publication date: August 12, 2010
    Applicants: Taisho Pharmaceutical Co., Ltd., Fumie Sato
    Inventors: Iwao ARAI, Nobuko Futaki, Yuki Hashimoto, Masanori Sugimoto
  • Patent number: 7737182
    Abstract: A method for or treating xerosis by applying a prostaglandin D receptor selective agonist to a mammal.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: June 15, 2010
    Assignees: Taisho Pharmaceutical Co., Ltd., Fumie Sato
    Inventors: Iwao Arai, Nobuko Futaki, Yuki Hashimoto, Masanori Sugimoto
  • Publication number: 20100123970
    Abstract: A disk drive. The disk drive includes a plurality of head-sliders, an actuator, a plurality of clearance adjustment sections, and a controller. Each head-slider includes a slider and a magnetic-recording head on the slider for accessing a disk for storing data. The plurality of head-sliders is secured to the actuator that is configured to move the plurality of head-sliders concurrently. Each clearance adjustment section corresponds to each head-slider of the plurality of head-sliders and adjusts a clearance of the corresponding head-slider. In addition, the controller is configured to position the actuator by servo control with a first head-slider selected from the plurality of head-sliders, to change a clearance of a second head-slider different from the first head-slider by controlling a clearance adjustment section of the second head-slider to bring the second head-slider into contact with a disk, and to detect the contact to measure the clearance of the second head-slider.
    Type: Application
    Filed: November 13, 2009
    Publication date: May 20, 2010
    Inventors: Manabu Saikawa, Atsushi Takeichi, Yuki Hashimoto, Kenji Kuroki, Mitsuhiro Shoda
  • Publication number: 20050192357
    Abstract: A method for preventing or treating xerosis which comprises applying a prostaglandin D receptor selective agonist to a mammal.
    Type: Application
    Filed: February 4, 2005
    Publication date: September 1, 2005
    Inventors: Iwao Arai, Nobuko Futaki, Yuki Hashimoto, Masanori Sugimoto
  • Publication number: 20030081482
    Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line/BL, a second transistor having the drain thereof connected to the bit line/BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.
    Type: Application
    Filed: May 24, 2000
    Publication date: May 1, 2003
    Inventors: Tadahiro Omata, Hidenori Uehara, Yuki Hashimoto, Shinya Takahashi
  • Patent number: 6433523
    Abstract: A system supply voltage, supplied from an external supply circuit, is lowered to generate an internal supply voltage for an internal circuit when the system supply voltage is higher than a breakdown voltage of the internal circuit. The system supply voltage is directly supplied to the internal circuit when the system supply voltage is not higher than the breakdown voltage of the internal circuit.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: August 13, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yuki Hashimoto
  • Publication number: 20020060894
    Abstract: Because a semiconductor relay system of this invention comprises an across-element voltage detecting circuit 116 which delivers an across-element voltage detection signal depending on the presence/absence of an across-element voltage exceeding a predetermined threshold; an element driving circuit 112 for delivering an element driving signal in response to a control input signal; a logic-based judgement circuit 119 for delivering a logic-based judgement signal depending on the presence/absence of an across-element voltage detection signal; and a filtration circuit for removing a logic-based judgement signal of external disturbing elements to produce an element safety check signal, it is possible to reliably detect the disorder of a triac 114.
    Type: Application
    Filed: November 15, 2001
    Publication date: May 23, 2002
    Applicant: OMRON CORPORATION
    Inventors: Kenji Horibata, Teruyuki Nakayama, Toshiyuki Nakamura, Takaaki Yamada, Yuki Hashimoto, Kazuhiro Harada
  • Publication number: 20020008500
    Abstract: A system supply voltage, supplied from an external supply circuit, is lowered to generate an internal supply voltage for an internal circuit when the system supply voltage is higher than a breakdown voltage of the internal circuit. The system supply voltage is directly supplied to the internal circuit when the system supply voltage is not higher than the breakdown voltage of the internal circuit.
    Type: Application
    Filed: February 1, 2001
    Publication date: January 24, 2002
    Inventor: Yuki Hashimoto
  • Publication number: 20010026489
    Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line /BL, a second transistor having the drain thereof connected to the bit line /BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.
    Type: Application
    Filed: June 6, 2001
    Publication date: October 4, 2001
    Inventors: Tadahiro Omata, Hidenori Uehara, Yuki Hashimoto, Shinya Takahashi
  • Patent number: 6091095
    Abstract: A sense amplifier for amplifying the potential difference between paired bit lines has a first transistor having the drain thereof connected to a bit line BL and the gate thereof connected to a bit line /BL, a second transistor having the drain thereof connected to the bit line /BL and the gate thereof connected to the bit line BL, and a third transistor and a fourth transistor provided in association with the first and second transistors, an identical sense amplifier actuating signal being applied to the gates thereof.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: July 18, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Tadahiro Omata, Hidenori Uehara, Yuki Hashimoto, Shinya Takahashi
  • Patent number: 5942809
    Abstract: An apparatus and method for generating an internal supply voltage for a semiconductor integrated circuit, includes a first voltage generator which generates a voltage in response to a predetermined characteristic of the semiconductor integrated circuit, a second voltage generator which generates a second voltage from a reference voltage generator, and a selecting circuit which selects from among the first and second voltage. The selected voltage is suppled to an internal supply voltage generator which generates therefrom an internal supply voltage for the semiconductor integrated circuit. The first voltage is selected for regulating the internal supply voltage, being controlled in level according to the characteristic of the semiconductor integrated circuit.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: August 24, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yuki Hashimoto
  • Patent number: 5856756
    Abstract: An internal voltage generating circuit for generating an internal voltage VINT from an input external voltage VEXT is provided to stabilize the internal voltage. When the external voltage VEXT is less than or equal to a first boundary voltage VT1 or a second boundary voltage VT2 (>VT1), a constant voltage VINTN independent on the external voltage VEXT, which is produced by a constant voltage generator is outputted therefrom. When the external voltage VEXT is greater than or equal to the first boundary voltage VT1 or the second boundary voltage VT2, a variable voltage (>VINTN) linearly increased with an increase in VEXT, which is produced by a variable voltage generator, is outputted therefrom. When a detecting means detects that the external voltage VEXT has been increased to VT2 or higher, the characteristic of the internal voltage is switched from a constant voltage characteristic to a variable voltage characteristic.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: January 5, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Katsuhiko Sasahara, Yuki Hashimoto
  • Patent number: 5446694
    Abstract: A semiconductor memory device of the present invention comprises an internal power supplying circuit electrically connected to an external power supply having an external source potential and for supplying an internal potential lower than the external source potential, a precharging circuit for supplying a half potential of the internal potential to each of memory cells and bit lines, and a switching circuit electrically connected between each bit line and the precharging circuit and controlled based on an equalize signal output from a control circuit and having the same potential as the external source potential. The semiconductor memory device of such a type that even if a potential on each bit line increases excessively, such a potential does not exert an influence on each memory cell, can be realized owing to the above structure.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: August 29, 1995
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takayuki Tanaka, Junichi Suyama, Kazukiyo Fukudome, Yuki Hashimoto
  • Patent number: 5255223
    Abstract: In a semiconductor memory device comprising memory cells connected at the intersections of pairs of bit lines and word lines, sense amplifiers activated by the potentials on common nodes to amplify the potential differences between the respective pairs of the bit lines, an equalizing circuit activated by an equalizing signal to apply the potential on a power supply node to the pairs of bit lines, and a reference potential supplying circuit for generating a reference potential and supplying the reference potential to the power supply node through a switching circuit, a circuit is provided to block the application of the reference potential to the bit lines and the sense amplifier common nodes and to apply a negative potential to the bit lines. The word lines are held at the ground level, so the physical "0" is written into all the memory cells simultaneously.
    Type: Grant
    Filed: July 17, 1991
    Date of Patent: October 19, 1993
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takayuki Tanaka, Shinya Takahashi, Yuki Hashimoto, Toshiharu Watanabe