Abstract: An image reading device which reads an image to obtain an image signal includes: a scanning unit; a chassis member; a control unit provided in a position which does not move together with the scanning unit; and a flexible flat cable which connects the scanning unit to the control unit, includes one end attached to a side of the chassis member and a position other than the one end fixed to a position which does not move with the scanning unit, includes a range closer to the one end than the fixed position parallel to a moving direction of the scanning unit, and is arranged to extend from the one end to one side, be bent into a U-shape, enter between the scanning unit and the chassis member, and reach the fixed position, and the flexible flat cable includes a transmitting layer, a shielding layer, and a stress adjusting layer.

Abstract: An image reading device of the present invention includes a reading unit in which a lighting system and an optical system are mounted, a controller provided at a position where the controller does not transfer along with the reading unit, and a flexible flat cable that includes a curved portion and connects the reading unit with the controller. The lighting system includes an elongated light conductor extended in the main scanning direction and an end portion light source arranged at the end portion of the light conductor. The flexible flat cable is arranged on the outside of the optical system and on the lower side of the light conductor.

Abstract: Provided is a mobile terminal test apparatus that can shorten a carrier aggregation testing time. The mobile terminal test apparatus includes a call processing units 12-0 to 12-n that transmits and receives a wireless signal between each of the call processing units 12-0 to 12-n and a mobile terminal 2, and makes a call connection suitable for testing conditions as a component carrier between each of the call processing units 12-0 to 12-n and the mobile terminal 2, and a control unit 15 that causes the mobile terminal 2 to perform a handover, and that applies parameters for a SCC that is designated, as parameters for a PCC that is a handover destination, to the call processing unit 12-0 that corresponds to a PCC, and applies parameters for the pre-handover PCC to the call processing unit 12-n that corresponds to the SCC that are designated and thus connects the SCC.

Abstract: An image reading device which reads an image to obtain an image signal includes: a scanning unit; a chassis member; a control unit provided in a position which does not move together with the scanning unit; and a flexible flat cable which connects the scanning unit to the control unit, includes one end attached to a side of the chassis member and a position other than the one end fixed to a position which does not move with the scanning unit, includes a range closer to the one end than the fixed position parallel to a moving direction of the scanning unit, and is arranged to extend from the one end to one side, be bent into a U-shape, enter between the scanning unit and the chassis member, and reach the fixed position, and the flexible flat cable includes a transmitting layer, a shielding layer, and a stress adjusting layer.

Abstract: Provided is a mobile terminal test apparatus that can shorten a carrier aggregation testing time. The mobile terminal test apparatus includes a call processing units 12-0 to 12-n that transmits and receives a wireless signal between each of the call processing units 12-0 to 12-n and a mobile terminal 2, and makes a call connection suitable for testing conditions as a component carrier between each of the call processing units 12-0 to 12-n and the mobile terminal 2, and a control unit 15 that causes the mobile terminal 2 to perform a handover, and that applies parameters for a SCC that is designated, as parameters for a PCC that is a handover destination, to the call processing unit 12-0 that corresponds to a PCC, and applies parameters for the pre-handover PCC to the call processing unit 12-n that corresponds to the SCC that are designated and thus connects the SCC.

Abstract: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

Abstract: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

Abstract: The purpose of the present invention is to provide a better intestine immunomodulator. The intestine immunomodulator of the present invention comprises bacterial cells or a bacterial component of a Lactobacillus paracasei K71 strain having an international deposit No.: FERM BP-11098 as an active ingredient. Preferably, the intestine immunomodulator is used to facilitate production of secretory immunoglobulin A or to activate natural killer cells.

Abstract: The purpose of the present invention is to provide a better intestine immunomodulator. The intestine immunomodulator of the present invention comprises bacterial cells or a bacterial component of a Lactobacillus paracasei K71 strain having an international deposit No.: FERM BP-11098 as an active ingredient. Preferably, the intestine immunomodulator is used to facilitate production of secretory immunoglobulin A or to activate natural killer cells.

Abstract: Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: In order to reduce occurrence of a fetching error of a digital signal, caused by a power-source noise, there is provided a semiconductor device provided with a switching circuit for executing a switching operation according to a pulse control signal and a digital signal hold circuit for fetching a digital signal. The digital signal hold circuit includes a mask signal generation circuit for generating a mask signal from the pulse control signal, the mask signal being for use in keeping the digital signal from being fetched during a time period of power-source noise occurrence caused by the switching operation, and the digital signal is not fetched during the time period of power-source noise occurrence while the digital signal is fetched during a time period of power-source noise nonoccurrence.

Abstract: A noise reduction circuit includes first and second reset signal generation circuits that generate first and second reset signals that are activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high level or a low level is maintained, and first and second counter circuits that count an inverted signal of the clock signal, and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit that includes a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock, wherein the selector circuit selects and outputs any of: a signal fixed at a high level or a low level, and an output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: A noise reduction circuit includes first and second reset signal generation circuits that generate first and second reset signals that are activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high level or a low level is maintained, and first and second counter circuits that count an inverted signal of the clock signal, and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit that includes a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock, wherein the selector circuit selects and outputs any of: a signal fixed at a high level or a low level, and an output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit.

Abstract: A semiconductor integrated circuit device includes: a first power supply region, power supply to which is controlled; and a second power supply region connected with a first power supply region. The first power supply region includes: a floating preventing circuit configured to fix an output voltage from the first power supply region to the second power supply region to a ground voltage in synchronization with stop of power supply.